/*
 * Generated by gen_defines.py
 *
 * DTS input file:
 *   nrf5340pdk_nrf5340_cpuapp.dts.pre.tmp
 *
 * Directories with bindings:
 *   C:/ncs/nrf/dts/bindings, $ZEPHYR_BASE\dts\bindings
 *
 * Nodes in dependency order (ordinal and path):
 *   0   /
 *   1   /aliases
 *   2   /chosen
 *   3   /buttons
 *   4   /soc
 *   5   /soc/peripheral@50000000
 *   6   /soc/peripheral@50000000/gpio@842500
 *   7   /buttons/button_0
 *   8   /buttons/button_1
 *   9   /buttons/button_2
 *   10  /buttons/button_3
 *   11  /cpus
 *   12  /cpus/cpu@0
 *   13  /cpus/cpu@0/mpu@e000ed90
 *   14  /leds
 *   15  /leds/led_0
 *   16  /leds/led_1
 *   17  /leds/led_2
 *   18  /leds/led_3
 *   19  /reserved-memory
 *   20  /reserved-memory/image@20000000
 *   21  /reserved-memory/image_ns@20010000
 *   22  /reserved-memory/image_s@20000000
 *   23  /reserved-memory/memory@20070000
 *   24  /soc/ficr@ff0000
 *   25  /soc/interrupt-controller@e000e100
 *   26  /soc/gpiote@5000d000
 *   27  /soc/memory@20000000
 *   28  /soc/spu@50003000
 *   29  /soc/timer@e000e010
 *   30  /soc/uicr@ff8000
 *   31  /soc/crypto@50844000
 *   32  /soc/crypto@50844000/crypto@50845000
 *   33  /soc/peripheral@50000000/adc@e000
 *   34  /soc/peripheral@50000000/clock@5000
 *   35  /soc/peripheral@50000000/dppic@17000
 *   36  /soc/peripheral@50000000/egu@1b000
 *   37  /soc/peripheral@50000000/egu@1c000
 *   38  /soc/peripheral@50000000/egu@1d000
 *   39  /soc/peripheral@50000000/egu@1e000
 *   40  /soc/peripheral@50000000/egu@1f000
 *   41  /soc/peripheral@50000000/egu@20000
 *   42  /soc/peripheral@50000000/gpio@842800
 *   43  /soc/peripheral@50000000/i2c@8000
 *   44  /soc/peripheral@50000000/i2c@9000
 *   45  /soc/peripheral@50000000/i2c@b000
 *   46  /soc/peripheral@50000000/i2c@c000
 *   47  /soc/peripheral@50000000/i2s@28000
 *   48  /soc/peripheral@50000000/ipc@2a000
 *   49  /soc/peripheral@50000000/kmu@39000
 *   50  /soc/peripheral@50000000/pdm@26000
 *   51  /soc/peripheral@50000000/power@5000
 *   52  /soc/peripheral@50000000/pwm@21000
 *   53  /soc/peripheral@50000000/pwm@22000
 *   54  /soc/peripheral@50000000/pwm@23000
 *   55  /soc/peripheral@50000000/pwm@24000
 *   56  /soc/peripheral@50000000/regulator@4000
 *   57  /soc/peripheral@50000000/rtc@14000
 *   58  /soc/peripheral@50000000/rtc@15000
 *   59  /soc/peripheral@50000000/spi@8000
 *   60  /soc/peripheral@50000000/spi@9000
 *   61  /soc/peripheral@50000000/spi@a000
 *   62  /soc/peripheral@50000000/spi@b000
 *   63  /soc/peripheral@50000000/spi@c000
 *   64  /soc/peripheral@50000000/timer@f000
 *   65  /soc/peripheral@50000000/timer@10000
 *   66  /soc/peripheral@50000000/timer@11000
 *   67  /soc/peripheral@50000000/uart@8000
 *   68  /soc/peripheral@50000000/uart@9000
 *   69  /soc/peripheral@50000000/uart@b000
 *   70  /soc/peripheral@50000000/uart@c000
 *   71  /soc/peripheral@50000000/vmc@81000
 *   72  /soc/peripheral@50000000/watchdog@18000
 *   73  /soc/peripheral@50000000/watchdog@19000
 *   74  /soc/peripheral@50000000/flash-controller@39000
 *   75  /soc/peripheral@50000000/flash-controller@39000/flash@0
 *   76  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions
 *   77  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0
 *   78  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000
 *   79  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@40000
 *   80  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@80000
 *   81  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@b0000
 *   82  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f0000
 *   83  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@fa000
 *
 * Definitions derived from these nodes in dependency order are next,
 * followed by /chosen nodes.
 */

/*
 * Devicetree node: /
 *
 * Node's generated path identifier: DT_N
 *
 * Dependency Ordinal: 0
 *
 * Supports:
 *   1   /aliases
 *   3   /buttons
 *   2   /chosen
 *   11  /cpus
 *   14  /leds
 *   19  /reserved-memory
 *   4   /soc
 */
#define DT_N_FOREACH_CHILD(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_cpus) fn(DT_N_S_leds) fn(DT_N_S_buttons) fn(DT_N_S_reserved_memory)

/* Existence and alternate IDs: */
#define DT_N_EXISTS 1
#define DT_N_INST_0_nordic_nrf5340_pdk_nrf5340_cpuapp DT_N
#define DT_N_INST_0_nordic_nrf5340_cpuapp_qkaa        DT_N
#define DT_N_INST_0_nordic_nrf5340_cpuapp             DT_N

/* Special property macros: */
#define DT_N_REG_NUM 0
#define DT_N_IRQ_NUM 0
#define DT_N_COMPAT_MATCHES_nordic_nrf5340_pdk_nrf5340_cpuapp 1
#define DT_N_COMPAT_MATCHES_nordic_nrf5340_cpuapp_qkaa 1
#define DT_N_COMPAT_MATCHES_nordic_nrf5340_cpuapp 1
#define DT_N_STATUS_okay 1

/* Generic property macros: */
#define DT_N_P_compatible {"nordic,nrf5340-pdk-nrf5340-cpuapp", "nordic,nrf5340-cpuapp-qkaa", "nordic,nrf5340-cpuapp"}
#define DT_N_P_compatible_IDX_0 "nordic,nrf5340-pdk-nrf5340-cpuapp"
#define DT_N_P_compatible_IDX_1 "nordic,nrf5340-cpuapp-qkaa"
#define DT_N_P_compatible_IDX_2 "nordic,nrf5340-cpuapp"
#define DT_N_P_compatible_LEN 3
#define DT_N_P_compatible_EXISTS 1

/*
 * Devicetree node: /aliases
 *
 * Node's generated path identifier: DT_N_S_aliases
 *
 * Dependency Ordinal: 1
 *
 * Requires:
 *   0   /
 */

/* Node parent (/) identifier: */
#define DT_N_S_aliases_PARENT DT_N
#define DT_N_S_aliases_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_aliases_EXISTS 1

/* Special property macros: */
#define DT_N_S_aliases_REG_NUM 0
#define DT_N_S_aliases_IRQ_NUM 0
#define DT_N_S_aliases_STATUS_okay 1

/* (No generic property macros) */

/*
 * Devicetree node: /chosen
 *
 * Node's generated path identifier: DT_N_S_chosen
 *
 * Dependency Ordinal: 2
 *
 * Requires:
 *   0   /
 */

/* Node parent (/) identifier: */
#define DT_N_S_chosen_PARENT DT_N
#define DT_N_S_chosen_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_chosen_EXISTS 1

/* Special property macros: */
#define DT_N_S_chosen_REG_NUM 0
#define DT_N_S_chosen_IRQ_NUM 0
#define DT_N_S_chosen_STATUS_okay 1

/* (No generic property macros) */

/*
 * Devicetree node: /buttons
 *
 * Node's generated path identifier: DT_N_S_buttons
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * Dependency Ordinal: 3
 *
 * Requires:
 *   0   /
 *
 * Supports:
 *   7   /buttons/button_0
 *   8   /buttons/button_1
 *   9   /buttons/button_2
 *   10  /buttons/button_3
 *
 * Description:
 *   GPIO KEYS parent node
 */

/* Node parent (/) identifier: */
#define DT_N_S_buttons_PARENT DT_N
#define DT_N_S_buttons_FOREACH_CHILD(fn) fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2) fn(DT_N_S_buttons_S_button_3)

/* Existence and alternate IDs: */
#define DT_N_S_buttons_EXISTS 1
#define DT_N_INST_0_gpio_keys DT_N_S_buttons

/* Special property macros: */
#define DT_N_S_buttons_REG_NUM 0
#define DT_N_S_buttons_IRQ_NUM 0
#define DT_N_S_buttons_COMPAT_MATCHES_gpio_keys 1
#define DT_N_S_buttons_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_buttons_P_compatible {"gpio-keys"}
#define DT_N_S_buttons_P_compatible_IDX_0 "gpio-keys"
#define DT_N_S_buttons_P_compatible_LEN 1
#define DT_N_S_buttons_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc
 *
 * Node's generated path identifier: DT_N_S_soc
 *
 * Dependency Ordinal: 4
 *
 * Requires:
 *   0   /
 *
 * Supports:
 *   31  /soc/crypto@50844000
 *   24  /soc/ficr@ff0000
 *   26  /soc/gpiote@5000d000
 *   25  /soc/interrupt-controller@e000e100
 *   27  /soc/memory@20000000
 *   5   /soc/peripheral@50000000
 *   28  /soc/spu@50003000
 *   29  /soc/timer@e000e010
 *   30  /soc/uicr@ff8000
 */

/* Node parent (/) identifier: */
#define DT_N_S_soc_PARENT DT_N
#define DT_N_S_soc_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_50000000) fn(DT_N_S_soc_S_crypto_50844000) fn(DT_N_S_soc_S_gpiote_5000d000) fn(DT_N_S_soc_S_spu_50003000) fn(DT_N_S_soc_S_ficr_ff0000) fn(DT_N_S_soc_S_uicr_ff8000)

/* Existence and alternate IDs: */
#define DT_N_S_soc_EXISTS 1
#define DT_N_INST_0_nordic_nrf5340_cpu0_qkaa DT_N_S_soc
#define DT_N_INST_0_nordic_nrf5340_cpu0      DT_N_S_soc
#define DT_N_INST_0_nordic_nrf53             DT_N_S_soc
#define DT_N_INST_0_simple_bus               DT_N_S_soc

/* Special property macros: */
#define DT_N_S_soc_REG_NUM 0
#define DT_N_S_soc_IRQ_NUM 0
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf5340_cpu0_qkaa 1
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf5340_cpu0 1
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf53 1
#define DT_N_S_soc_COMPAT_MATCHES_simple_bus 1
#define DT_N_S_soc_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_P_compatible {"nordic,nRF5340-CPU0-QKAA", "nordic,nRF5340-CPU0", "nordic,nRF53", "simple-bus"}
#define DT_N_S_soc_P_compatible_IDX_0 "nordic,nRF5340-CPU0-QKAA"
#define DT_N_S_soc_P_compatible_IDX_1 "nordic,nRF5340-CPU0"
#define DT_N_S_soc_P_compatible_IDX_2 "nordic,nRF53"
#define DT_N_S_soc_P_compatible_IDX_3 "simple-bus"
#define DT_N_S_soc_P_compatible_LEN 4
#define DT_N_S_soc_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000
 *
 * Dependency Ordinal: 5
 *
 * Requires:
 *   4   /soc
 *
 * Supports:
 *   33  /soc/peripheral@50000000/adc@e000
 *   34  /soc/peripheral@50000000/clock@5000
 *   35  /soc/peripheral@50000000/dppic@17000
 *   36  /soc/peripheral@50000000/egu@1b000
 *   37  /soc/peripheral@50000000/egu@1c000
 *   38  /soc/peripheral@50000000/egu@1d000
 *   39  /soc/peripheral@50000000/egu@1e000
 *   40  /soc/peripheral@50000000/egu@1f000
 *   41  /soc/peripheral@50000000/egu@20000
 *   74  /soc/peripheral@50000000/flash-controller@39000
 *   6   /soc/peripheral@50000000/gpio@842500
 *   42  /soc/peripheral@50000000/gpio@842800
 *   43  /soc/peripheral@50000000/i2c@8000
 *   44  /soc/peripheral@50000000/i2c@9000
 *   45  /soc/peripheral@50000000/i2c@b000
 *   46  /soc/peripheral@50000000/i2c@c000
 *   47  /soc/peripheral@50000000/i2s@28000
 *   48  /soc/peripheral@50000000/ipc@2a000
 *   49  /soc/peripheral@50000000/kmu@39000
 *   50  /soc/peripheral@50000000/pdm@26000
 *   51  /soc/peripheral@50000000/power@5000
 *   52  /soc/peripheral@50000000/pwm@21000
 *   53  /soc/peripheral@50000000/pwm@22000
 *   54  /soc/peripheral@50000000/pwm@23000
 *   55  /soc/peripheral@50000000/pwm@24000
 *   56  /soc/peripheral@50000000/regulator@4000
 *   57  /soc/peripheral@50000000/rtc@14000
 *   58  /soc/peripheral@50000000/rtc@15000
 *   59  /soc/peripheral@50000000/spi@8000
 *   60  /soc/peripheral@50000000/spi@9000
 *   61  /soc/peripheral@50000000/spi@a000
 *   62  /soc/peripheral@50000000/spi@b000
 *   63  /soc/peripheral@50000000/spi@c000
 *   64  /soc/peripheral@50000000/timer@f000
 *   65  /soc/peripheral@50000000/timer@10000
 *   66  /soc/peripheral@50000000/timer@11000
 *   67  /soc/peripheral@50000000/uart@8000
 *   68  /soc/peripheral@50000000/uart@9000
 *   69  /soc/peripheral@50000000/uart@b000
 *   70  /soc/peripheral@50000000/uart@c000
 *   71  /soc/peripheral@50000000/vmc@81000
 *   72  /soc/peripheral@50000000/watchdog@18000
 *   73  /soc/peripheral@50000000/watchdog@19000
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_peripheral_50000000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_50000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_50000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2s_28000) fn(DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000) fn(DT_N_S_soc_S_peripheral_50000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_50000000_S_pdm_26000) fn(DT_N_S_soc_S_peripheral_50000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_50000000_S_vmc_81000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_uart_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_i2c_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_8000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_9000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_b000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_c000) fn(DT_N_S_soc_S_peripheral_50000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_22000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_23000) fn(DT_N_S_soc_S_peripheral_50000000_S_pwm_24000) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_50000000_S_gpio_842800) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_50000000_S_rtc_15000) fn(DT_N_S_soc_S_peripheral_50000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_timer_11000)

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_EXISTS 1

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_REG_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_STATUS_okay 1

/* (No generic property macros) */

/*
 * Devicetree node: /soc/peripheral@50000000/gpio@842500
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
 *
 * Binding (compatible = nordic,nrf-gpio):
 *   $ZEPHYR_BASE\dts\bindings\gpio\nordic,nrf-gpio.yaml
 *
 * Dependency Ordinal: 6
 *
 * Requires:
 *   5   /soc/peripheral@50000000
 *
 * Supports:
 *   7   /buttons/button_0
 *   8   /buttons/button_1
 *   9   /buttons/button_2
 *   10  /buttons/button_3
 *   15  /leds/led_0
 *   16  /leds/led_1
 *   17  /leds/led_2
 *   18  /leds/led_3
 *
 * Description:
 *   NRF5 GPIO node
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_EXISTS 1
#define DT_N_ALIAS_gpio_0           DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
#define DT_N_INST_0_nordic_nrf_gpio DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
#define DT_N_NODELABEL_gpio0        DT_N_S_soc_S_peripheral_50000000_S_gpio_842500

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_IDX_0_VAL_ADDRESS 1350837504 /* 0x50842500 */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_REG_IDX_0_VAL_SIZE 768 /* 0x300 */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_COMPAT_MATCHES_nordic_nrf_gpio 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg {8660224 /* 0x842500 */, 768 /* 0x300 */}
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_0 8660224
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_IDX_1 768
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_label "GPIO_0"
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpio_controller 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_ngpios 32
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible {"nordic,nrf-gpio"}
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_IDX_0 "nordic,nrf-gpio"
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842500_P_compatible_EXISTS 1

/*
 * Devicetree node: /buttons/button_0
 *
 * Node's generated path identifier: DT_N_S_buttons_S_button_0
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * Dependency Ordinal: 7
 *
 * Requires:
 *   3   /buttons
 *   6   /soc/peripheral@50000000/gpio@842500
 *
 * Description:
 *   GPIO KEYS child node
 */

/* Node parent (/buttons) identifier: */
#define DT_N_S_buttons_S_button_0_PARENT DT_N_S_buttons
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_buttons_S_button_0_EXISTS 1
#define DT_N_ALIAS_sw0         DT_N_S_buttons_S_button_0
#define DT_N_NODELABEL_button0 DT_N_S_buttons_S_button_0

/* Special property macros: */
#define DT_N_S_buttons_S_button_0_REG_NUM 0
#define DT_N_S_buttons_S_button_0_IRQ_NUM 0
#define DT_N_S_buttons_S_button_0_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_pin 23
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_buttons_S_button_0_P_gpios_LEN 1
#define DT_N_S_buttons_S_button_0_P_gpios_EXISTS 1
#define DT_N_S_buttons_S_button_0_P_label "Push button 1"
#define DT_N_S_buttons_S_button_0_P_label_EXISTS 1

/*
 * Devicetree node: /buttons/button_1
 *
 * Node's generated path identifier: DT_N_S_buttons_S_button_1
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * Dependency Ordinal: 8
 *
 * Requires:
 *   3   /buttons
 *   6   /soc/peripheral@50000000/gpio@842500
 *
 * Description:
 *   GPIO KEYS child node
 */

/* Node parent (/buttons) identifier: */
#define DT_N_S_buttons_S_button_1_PARENT DT_N_S_buttons
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_buttons_S_button_1_EXISTS 1
#define DT_N_ALIAS_sw1         DT_N_S_buttons_S_button_1
#define DT_N_NODELABEL_button1 DT_N_S_buttons_S_button_1

/* Special property macros: */
#define DT_N_S_buttons_S_button_1_REG_NUM 0
#define DT_N_S_buttons_S_button_1_IRQ_NUM 0
#define DT_N_S_buttons_S_button_1_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_pin 24
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_buttons_S_button_1_P_gpios_LEN 1
#define DT_N_S_buttons_S_button_1_P_gpios_EXISTS 1
#define DT_N_S_buttons_S_button_1_P_label "Push button 2"
#define DT_N_S_buttons_S_button_1_P_label_EXISTS 1

/*
 * Devicetree node: /buttons/button_2
 *
 * Node's generated path identifier: DT_N_S_buttons_S_button_2
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * Dependency Ordinal: 9
 *
 * Requires:
 *   3   /buttons
 *   6   /soc/peripheral@50000000/gpio@842500
 *
 * Description:
 *   GPIO KEYS child node
 */

/* Node parent (/buttons) identifier: */
#define DT_N_S_buttons_S_button_2_PARENT DT_N_S_buttons
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_buttons_S_button_2_EXISTS 1
#define DT_N_ALIAS_sw2         DT_N_S_buttons_S_button_2
#define DT_N_NODELABEL_button2 DT_N_S_buttons_S_button_2

/* Special property macros: */
#define DT_N_S_buttons_S_button_2_REG_NUM 0
#define DT_N_S_buttons_S_button_2_IRQ_NUM 0
#define DT_N_S_buttons_S_button_2_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_pin 8
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_buttons_S_button_2_P_gpios_LEN 1
#define DT_N_S_buttons_S_button_2_P_gpios_EXISTS 1
#define DT_N_S_buttons_S_button_2_P_label "Push button 3"
#define DT_N_S_buttons_S_button_2_P_label_EXISTS 1

/*
 * Devicetree node: /buttons/button_3
 *
 * Node's generated path identifier: DT_N_S_buttons_S_button_3
 *
 * Binding (compatible = gpio-keys):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-keys.yaml
 *
 * Dependency Ordinal: 10
 *
 * Requires:
 *   3   /buttons
 *   6   /soc/peripheral@50000000/gpio@842500
 *
 * Description:
 *   GPIO KEYS child node
 */

/* Node parent (/buttons) identifier: */
#define DT_N_S_buttons_S_button_3_PARENT DT_N_S_buttons
#define DT_N_S_buttons_S_button_3_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_buttons_S_button_3_EXISTS 1
#define DT_N_ALIAS_sw3         DT_N_S_buttons_S_button_3
#define DT_N_NODELABEL_button3 DT_N_S_buttons_S_button_3

/* Special property macros: */
#define DT_N_S_buttons_S_button_3_REG_NUM 0
#define DT_N_S_buttons_S_button_3_IRQ_NUM 0
#define DT_N_S_buttons_S_button_3_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_pin 9
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_flags 17
#define DT_N_S_buttons_S_button_3_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_buttons_S_button_3_P_gpios_LEN 1
#define DT_N_S_buttons_S_button_3_P_gpios_EXISTS 1
#define DT_N_S_buttons_S_button_3_P_label "Push button 4"
#define DT_N_S_buttons_S_button_3_P_label_EXISTS 1

/*
 * Devicetree node: /cpus
 *
 * Node's generated path identifier: DT_N_S_cpus
 *
 * Dependency Ordinal: 11
 *
 * Requires:
 *   0   /
 *
 * Supports:
 *   12  /cpus/cpu@0
 */

/* Node parent (/) identifier: */
#define DT_N_S_cpus_PARENT DT_N
#define DT_N_S_cpus_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0)

/* Existence and alternate IDs: */
#define DT_N_S_cpus_EXISTS 1

/* Special property macros: */
#define DT_N_S_cpus_REG_NUM 0
#define DT_N_S_cpus_IRQ_NUM 0
#define DT_N_S_cpus_STATUS_okay 1

/* (No generic property macros) */

/*
 * Devicetree node: /cpus/cpu@0
 *
 * Node's generated path identifier: DT_N_S_cpus_S_cpu_0
 *
 * Dependency Ordinal: 12
 *
 * Requires:
 *   11  /cpus
 *
 * Supports:
 *   13  /cpus/cpu@0/mpu@e000ed90
 */

/* Node parent (/cpus) identifier: */
#define DT_N_S_cpus_S_cpu_0_PARENT DT_N_S_cpus
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_cpu_0_EXISTS 1
#define DT_N_INST_0_arm_cortex_m33f DT_N_S_cpus_S_cpu_0

/* Special property macros: */
#define DT_N_S_cpus_S_cpu_0_REG_NUM 1
#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_cpus_S_cpu_0_IRQ_NUM 0
#define DT_N_S_cpus_S_cpu_0_COMPAT_MATCHES_arm_cortex_m33f 1
#define DT_N_S_cpus_S_cpu_0_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_cpus_S_cpu_0_P_compatible {"arm,cortex-m33f"}
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0 "arm,cortex-m33f"
#define DT_N_S_cpus_S_cpu_0_P_compatible_LEN 1
#define DT_N_S_cpus_S_cpu_0_P_compatible_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_reg {0 /* 0x0 */}
#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0 0
#define DT_N_S_cpus_S_cpu_0_P_reg_EXISTS 1

/*
 * Devicetree node: /cpus/cpu@0/mpu@e000ed90
 *
 * Node's generated path identifier: DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90
 *
 * Binding (compatible = arm,armv8m-mpu):
 *   $ZEPHYR_BASE\dts\bindings\mmu_mpu\arm,armv8m-mpu.yaml
 *
 * Dependency Ordinal: 13
 *
 * Requires:
 *   12  /cpus/cpu@0
 *
 * Description:
 *   ARMv8-M MPU (Memory Protection Unit)
 */

/* Node parent (/cpus/cpu@0) identifier: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PARENT DT_N_S_cpus_S_cpu_0
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_EXISTS 1
#define DT_N_INST_0_arm_armv8m_mpu DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90
#define DT_N_NODELABEL_mpu         DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90

/* Special property macros: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_NUM 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_ADDRESS 3758157200 /* 0xe000ed90 */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_SIZE 64 /* 0x40 */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_IRQ_NUM 0
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_MATCHES_arm_armv8m_mpu 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg {3758157200 /* 0xe000ed90 */, 64 /* 0x40 */}
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0 3758157200
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1 64
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_arm_num_mpu_regions 16
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_arm_num_mpu_regions_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible {"arm,armv8m-mpu"}
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0 "arm,armv8m-mpu"
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_LEN 1
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_EXISTS 1

/*
 * Devicetree node: /leds
 *
 * Node's generated path identifier: DT_N_S_leds
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-leds.yaml
 *
 * Dependency Ordinal: 14
 *
 * Requires:
 *   0   /
 *
 * Supports:
 *   15  /leds/led_0
 *   16  /leds/led_1
 *   17  /leds/led_2
 *   18  /leds/led_3
 *
 * Description:
 *   GPIO LEDs parent node
 */

/* Node parent (/) identifier: */
#define DT_N_S_leds_PARENT DT_N
#define DT_N_S_leds_FOREACH_CHILD(fn) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_leds_S_led_3)

/* Existence and alternate IDs: */
#define DT_N_S_leds_EXISTS 1
#define DT_N_INST_0_gpio_leds DT_N_S_leds

/* Special property macros: */
#define DT_N_S_leds_REG_NUM 0
#define DT_N_S_leds_IRQ_NUM 0
#define DT_N_S_leds_COMPAT_MATCHES_gpio_leds 1
#define DT_N_S_leds_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_leds_P_compatible {"gpio-leds"}
#define DT_N_S_leds_P_compatible_IDX_0 "gpio-leds"
#define DT_N_S_leds_P_compatible_LEN 1
#define DT_N_S_leds_P_compatible_EXISTS 1

/*
 * Devicetree node: /leds/led_0
 *
 * Node's generated path identifier: DT_N_S_leds_S_led_0
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-leds.yaml
 *
 * Dependency Ordinal: 15
 *
 * Requires:
 *   14  /leds
 *   6   /soc/peripheral@50000000/gpio@842500
 *
 * Description:
 *   GPIO LED child node
 */

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_0_PARENT DT_N_S_leds
#define DT_N_S_leds_S_led_0_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_0_EXISTS 1
#define DT_N_ALIAS_led0     DT_N_S_leds_S_led_0
#define DT_N_NODELABEL_led0 DT_N_S_leds_S_led_0

/* Special property macros: */
#define DT_N_S_leds_S_led_0_REG_NUM 0
#define DT_N_S_leds_S_led_0_IRQ_NUM 0
#define DT_N_S_leds_S_led_0_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin 28
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags 1
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_0_P_gpios_LEN 1
#define DT_N_S_leds_S_led_0_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_0_P_label "Green LED 0"
#define DT_N_S_leds_S_led_0_P_label_EXISTS 1

/*
 * Devicetree node: /leds/led_1
 *
 * Node's generated path identifier: DT_N_S_leds_S_led_1
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-leds.yaml
 *
 * Dependency Ordinal: 16
 *
 * Requires:
 *   14  /leds
 *   6   /soc/peripheral@50000000/gpio@842500
 *
 * Description:
 *   GPIO LED child node
 */

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_1_PARENT DT_N_S_leds
#define DT_N_S_leds_S_led_1_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_1_EXISTS 1
#define DT_N_ALIAS_led1     DT_N_S_leds_S_led_1
#define DT_N_NODELABEL_led1 DT_N_S_leds_S_led_1

/* Special property macros: */
#define DT_N_S_leds_S_led_1_REG_NUM 0
#define DT_N_S_leds_S_led_1_IRQ_NUM 0
#define DT_N_S_leds_S_led_1_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin 29
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags 1
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_1_P_gpios_LEN 1
#define DT_N_S_leds_S_led_1_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_1_P_label "Green LED 1"
#define DT_N_S_leds_S_led_1_P_label_EXISTS 1

/*
 * Devicetree node: /leds/led_2
 *
 * Node's generated path identifier: DT_N_S_leds_S_led_2
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-leds.yaml
 *
 * Dependency Ordinal: 17
 *
 * Requires:
 *   14  /leds
 *   6   /soc/peripheral@50000000/gpio@842500
 *
 * Description:
 *   GPIO LED child node
 */

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_2_PARENT DT_N_S_leds
#define DT_N_S_leds_S_led_2_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_2_EXISTS 1
#define DT_N_ALIAS_led2     DT_N_S_leds_S_led_2
#define DT_N_NODELABEL_led2 DT_N_S_leds_S_led_2

/* Special property macros: */
#define DT_N_S_leds_S_led_2_REG_NUM 0
#define DT_N_S_leds_S_led_2_IRQ_NUM 0
#define DT_N_S_leds_S_led_2_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin 30
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags 1
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_2_P_gpios_LEN 1
#define DT_N_S_leds_S_led_2_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_2_P_label "Green LED 2"
#define DT_N_S_leds_S_led_2_P_label_EXISTS 1

/*
 * Devicetree node: /leds/led_3
 *
 * Node's generated path identifier: DT_N_S_leds_S_led_3
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE\dts\bindings\gpio\gpio-leds.yaml
 *
 * Dependency Ordinal: 18
 *
 * Requires:
 *   14  /leds
 *   6   /soc/peripheral@50000000/gpio@842500
 *
 * Description:
 *   GPIO LED child node
 */

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_3_PARENT DT_N_S_leds
#define DT_N_S_leds_S_led_3_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_3_EXISTS 1
#define DT_N_ALIAS_led3     DT_N_S_leds_S_led_3
#define DT_N_NODELABEL_led3 DT_N_S_leds_S_led_3

/* Special property macros: */
#define DT_N_S_leds_S_led_3_REG_NUM 0
#define DT_N_S_leds_S_led_3_IRQ_NUM 0
#define DT_N_S_leds_S_led_3_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_PH DT_N_S_soc_S_peripheral_50000000_S_gpio_842500
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_pin 31
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_flags 1
#define DT_N_S_leds_S_led_3_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_3_P_gpios_LEN 1
#define DT_N_S_leds_S_led_3_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_3_P_label "Green LED 3"
#define DT_N_S_leds_S_led_3_P_label_EXISTS 1

/*
 * Devicetree node: /reserved-memory
 *
 * Node's generated path identifier: DT_N_S_reserved_memory
 *
 * Dependency Ordinal: 19
 *
 * Requires:
 *   0   /
 *
 * Supports:
 *   20  /reserved-memory/image@20000000
 *   21  /reserved-memory/image_ns@20010000
 *   22  /reserved-memory/image_s@20000000
 *   23  /reserved-memory/memory@20070000
 */

/* Node parent (/) identifier: */
#define DT_N_S_reserved_memory_PARENT DT_N
#define DT_N_S_reserved_memory_FOREACH_CHILD(fn) fn(DT_N_S_reserved_memory_S_image_20000000) fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_ns_20010000) fn(DT_N_S_reserved_memory_S_memory_20070000)

/* Existence and alternate IDs: */
#define DT_N_S_reserved_memory_EXISTS 1

/* Special property macros: */
#define DT_N_S_reserved_memory_REG_NUM 0
#define DT_N_S_reserved_memory_IRQ_NUM 0
#define DT_N_S_reserved_memory_STATUS_okay 1

/* (No generic property macros) */

/*
 * Devicetree node: /reserved-memory/image@20000000
 *
 * Node's generated path identifier: DT_N_S_reserved_memory_S_image_20000000
 *
 * Dependency Ordinal: 20
 *
 * Requires:
 *   19  /reserved-memory
 */

/* Node parent (/reserved-memory) identifier: */
#define DT_N_S_reserved_memory_S_image_20000000_PARENT DT_N_S_reserved_memory
#define DT_N_S_reserved_memory_S_image_20000000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_reserved_memory_S_image_20000000_EXISTS 1
#define DT_N_NODELABEL_sram0_image DT_N_S_reserved_memory_S_image_20000000

/* Special property macros: */
#define DT_N_S_reserved_memory_S_image_20000000_REG_NUM 1
#define DT_N_S_reserved_memory_S_image_20000000_REG_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */
#define DT_N_S_reserved_memory_S_image_20000000_REG_IDX_0_VAL_SIZE 458752 /* 0x70000 */
#define DT_N_S_reserved_memory_S_image_20000000_IRQ_NUM 0
#define DT_N_S_reserved_memory_S_image_20000000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_reserved_memory_S_image_20000000_P_reg {536870912 /* 0x20000000 */, 458752 /* 0x70000 */}
#define DT_N_S_reserved_memory_S_image_20000000_P_reg_IDX_0 536870912
#define DT_N_S_reserved_memory_S_image_20000000_P_reg_IDX_1 458752
#define DT_N_S_reserved_memory_S_image_20000000_P_reg_EXISTS 1

/*
 * Devicetree node: /reserved-memory/image_ns@20010000
 *
 * Node's generated path identifier: DT_N_S_reserved_memory_S_image_ns_20010000
 *
 * Dependency Ordinal: 21
 *
 * Requires:
 *   19  /reserved-memory
 */

/* Node parent (/reserved-memory) identifier: */
#define DT_N_S_reserved_memory_S_image_ns_20010000_PARENT DT_N_S_reserved_memory
#define DT_N_S_reserved_memory_S_image_ns_20010000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_reserved_memory_S_image_ns_20010000_EXISTS 1
#define DT_N_NODELABEL_sram0_ns DT_N_S_reserved_memory_S_image_ns_20010000

/* Special property macros: */
#define DT_N_S_reserved_memory_S_image_ns_20010000_REG_NUM 1
#define DT_N_S_reserved_memory_S_image_ns_20010000_REG_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_ns_20010000_REG_IDX_0_VAL_ADDRESS 536936448 /* 0x20010000 */
#define DT_N_S_reserved_memory_S_image_ns_20010000_REG_IDX_0_VAL_SIZE 393216 /* 0x60000 */
#define DT_N_S_reserved_memory_S_image_ns_20010000_IRQ_NUM 0
#define DT_N_S_reserved_memory_S_image_ns_20010000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_reserved_memory_S_image_ns_20010000_P_reg {536936448 /* 0x20010000 */, 393216 /* 0x60000 */}
#define DT_N_S_reserved_memory_S_image_ns_20010000_P_reg_IDX_0 536936448
#define DT_N_S_reserved_memory_S_image_ns_20010000_P_reg_IDX_1 393216
#define DT_N_S_reserved_memory_S_image_ns_20010000_P_reg_EXISTS 1

/*
 * Devicetree node: /reserved-memory/image_s@20000000
 *
 * Node's generated path identifier: DT_N_S_reserved_memory_S_image_s_20000000
 *
 * Dependency Ordinal: 22
 *
 * Requires:
 *   19  /reserved-memory
 */

/* Node parent (/reserved-memory) identifier: */
#define DT_N_S_reserved_memory_S_image_s_20000000_PARENT DT_N_S_reserved_memory
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_reserved_memory_S_image_s_20000000_EXISTS 1
#define DT_N_NODELABEL_sram0_s DT_N_S_reserved_memory_S_image_s_20000000

/* Special property macros: */
#define DT_N_S_reserved_memory_S_image_s_20000000_REG_NUM 1
#define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */
#define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_VAL_SIZE 65536 /* 0x10000 */
#define DT_N_S_reserved_memory_S_image_s_20000000_IRQ_NUM 0
#define DT_N_S_reserved_memory_S_image_s_20000000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg {536870912 /* 0x20000000 */, 65536 /* 0x10000 */}
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_0 536870912
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_1 65536
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_EXISTS 1

/*
 * Devicetree node: /reserved-memory/memory@20070000
 *
 * Node's generated path identifier: DT_N_S_reserved_memory_S_memory_20070000
 *
 * Dependency Ordinal: 23
 *
 * Requires:
 *   19  /reserved-memory
 */

/* Node parent (/reserved-memory) identifier: */
#define DT_N_S_reserved_memory_S_memory_20070000_PARENT DT_N_S_reserved_memory
#define DT_N_S_reserved_memory_S_memory_20070000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_reserved_memory_S_memory_20070000_EXISTS 1
#define DT_N_NODELABEL_sram0_shared DT_N_S_reserved_memory_S_memory_20070000

/* Special property macros: */
#define DT_N_S_reserved_memory_S_memory_20070000_REG_NUM 1
#define DT_N_S_reserved_memory_S_memory_20070000_REG_IDX_0_EXISTS 1
#define DT_N_S_reserved_memory_S_memory_20070000_REG_IDX_0_VAL_ADDRESS 537329664 /* 0x20070000 */
#define DT_N_S_reserved_memory_S_memory_20070000_REG_IDX_0_VAL_SIZE 65536 /* 0x10000 */
#define DT_N_S_reserved_memory_S_memory_20070000_IRQ_NUM 0
#define DT_N_S_reserved_memory_S_memory_20070000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_reserved_memory_S_memory_20070000_P_reg {537329664 /* 0x20070000 */, 65536 /* 0x10000 */}
#define DT_N_S_reserved_memory_S_memory_20070000_P_reg_IDX_0 537329664
#define DT_N_S_reserved_memory_S_memory_20070000_P_reg_IDX_1 65536
#define DT_N_S_reserved_memory_S_memory_20070000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/ficr@ff0000
 *
 * Node's generated path identifier: DT_N_S_soc_S_ficr_ff0000
 *
 * Binding (compatible = nordic,nrf-ficr):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-ficr.yaml
 *
 * Dependency Ordinal: 24
 *
 * Requires:
 *   4   /soc
 *
 * Description:
 *   Nordic FICR (Factory Information Configuration Registers)
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_ficr_ff0000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_ficr_ff0000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_ficr_ff0000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_ficr DT_N_S_soc_S_ficr_ff0000
#define DT_N_NODELABEL_ficr         DT_N_S_soc_S_ficr_ff0000

/* Special property macros: */
#define DT_N_S_soc_S_ficr_ff0000_REG_NUM 1
#define DT_N_S_soc_S_ficr_ff0000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_REG_IDX_0_VAL_ADDRESS 16711680 /* 0xff0000 */
#define DT_N_S_soc_S_ficr_ff0000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_ficr_ff0000_IRQ_NUM 0
#define DT_N_S_soc_S_ficr_ff0000_COMPAT_MATCHES_nordic_nrf_ficr 1
#define DT_N_S_soc_S_ficr_ff0000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_ficr_ff0000_P_reg {16711680 /* 0xff0000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_0 16711680
#define DT_N_S_soc_S_ficr_ff0000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_ficr_ff0000_P_reg_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_P_status "okay"
#define DT_N_S_soc_S_ficr_ff0000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_ficr_ff0000_P_status_EXISTS 1
#define DT_N_S_soc_S_ficr_ff0000_P_compatible {"nordic,nrf-ficr"}
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_IDX_0 "nordic,nrf-ficr"
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_LEN 1
#define DT_N_S_soc_S_ficr_ff0000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/interrupt-controller@e000e100
 *
 * Node's generated path identifier: DT_N_S_soc_S_interrupt_controller_e000e100
 *
 * Binding (compatible = arm,v8m-nvic):
 *   $ZEPHYR_BASE\dts\bindings\interrupt-controller\arm,v8m-nvic.yaml
 *
 * Dependency Ordinal: 25
 *
 * Requires:
 *   4   /soc
 *
 * Supports:
 *   26  /soc/gpiote@5000d000
 *   28  /soc/spu@50003000
 *   32  /soc/crypto@50844000/crypto@50845000
 *   33  /soc/peripheral@50000000/adc@e000
 *   34  /soc/peripheral@50000000/clock@5000
 *   36  /soc/peripheral@50000000/egu@1b000
 *   37  /soc/peripheral@50000000/egu@1c000
 *   38  /soc/peripheral@50000000/egu@1d000
 *   39  /soc/peripheral@50000000/egu@1e000
 *   40  /soc/peripheral@50000000/egu@1f000
 *   41  /soc/peripheral@50000000/egu@20000
 *   43  /soc/peripheral@50000000/i2c@8000
 *   44  /soc/peripheral@50000000/i2c@9000
 *   45  /soc/peripheral@50000000/i2c@b000
 *   46  /soc/peripheral@50000000/i2c@c000
 *   47  /soc/peripheral@50000000/i2s@28000
 *   48  /soc/peripheral@50000000/ipc@2a000
 *   49  /soc/peripheral@50000000/kmu@39000
 *   50  /soc/peripheral@50000000/pdm@26000
 *   51  /soc/peripheral@50000000/power@5000
 *   52  /soc/peripheral@50000000/pwm@21000
 *   53  /soc/peripheral@50000000/pwm@22000
 *   54  /soc/peripheral@50000000/pwm@23000
 *   55  /soc/peripheral@50000000/pwm@24000
 *   57  /soc/peripheral@50000000/rtc@14000
 *   58  /soc/peripheral@50000000/rtc@15000
 *   59  /soc/peripheral@50000000/spi@8000
 *   60  /soc/peripheral@50000000/spi@9000
 *   61  /soc/peripheral@50000000/spi@a000
 *   62  /soc/peripheral@50000000/spi@b000
 *   63  /soc/peripheral@50000000/spi@c000
 *   64  /soc/peripheral@50000000/timer@f000
 *   65  /soc/peripheral@50000000/timer@10000
 *   66  /soc/peripheral@50000000/timer@11000
 *   67  /soc/peripheral@50000000/uart@8000
 *   68  /soc/peripheral@50000000/uart@9000
 *   69  /soc/peripheral@50000000/uart@b000
 *   70  /soc/peripheral@50000000/uart@c000
 *   72  /soc/peripheral@50000000/watchdog@18000
 *   73  /soc/peripheral@50000000/watchdog@19000
 *
 * Description:
 *   ARMv8-M NVIC (Nested Vectored Interrupt Controller)
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_PARENT DT_N_S_soc
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_EXISTS 1
#define DT_N_INST_0_arm_v8m_nvic DT_N_S_soc_S_interrupt_controller_e000e100
#define DT_N_NODELABEL_nvic      DT_N_S_soc_S_interrupt_controller_e000e100

/* Special property macros: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_NUM 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_ADDRESS 3758153984 /* 0xe000e100 */
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_SIZE 3072 /* 0xc00 */
#define DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_NUM 0
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MATCHES_arm_v8m_nvic 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg {3758153984 /* 0xe000e100 */, 3072 /* 0xc00 */}
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0 3758153984
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1 3072
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits 3
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible {"arm,v8m-nvic"}
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0 "arm,v8m-nvic"
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_LEN 1
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/gpiote@5000d000
 *
 * Node's generated path identifier: DT_N_S_soc_S_gpiote_5000d000
 *
 * Binding (compatible = nordic,nrf-gpiote):
 *   $ZEPHYR_BASE\dts\bindings\gpio\nordic,nrf-gpiote.yaml
 *
 * Dependency Ordinal: 26
 *
 * Requires:
 *   4   /soc
 *   25  /soc/interrupt-controller@e000e100
 *
 * Description:
 *   NRF5 GPIOTE node
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_gpiote_5000d000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_gpiote_5000d000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_gpiote_5000d000_EXISTS 1
#define DT_N_ALIAS_gpiote_0           DT_N_S_soc_S_gpiote_5000d000
#define DT_N_INST_0_nordic_nrf_gpiote DT_N_S_soc_S_gpiote_5000d000
#define DT_N_NODELABEL_gpiote         DT_N_S_soc_S_gpiote_5000d000

/* Special property macros: */
#define DT_N_S_soc_S_gpiote_5000d000_REG_NUM 1
#define DT_N_S_soc_S_gpiote_5000d000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_REG_IDX_0_VAL_ADDRESS 1342230528 /* 0x5000d000 */
#define DT_N_S_soc_S_gpiote_5000d000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_NUM 1
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_irq 13
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_priority 5
#define DT_N_S_soc_S_gpiote_5000d000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_COMPAT_MATCHES_nordic_nrf_gpiote 1
#define DT_N_S_soc_S_gpiote_5000d000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_gpiote_5000d000_P_reg {1342230528 /* 0x5000d000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_0 1342230528
#define DT_N_S_soc_S_gpiote_5000d000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_gpiote_5000d000_P_reg_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_interrupts {13 /* 0xd */, 5 /* 0x5 */}
#define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_0 13
#define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_IDX_1 5
#define DT_N_S_soc_S_gpiote_5000d000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_label "GPIOTE_0"
#define DT_N_S_soc_S_gpiote_5000d000_P_label_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_status "okay"
#define DT_N_S_soc_S_gpiote_5000d000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_gpiote_5000d000_P_status_EXISTS 1
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible {"nordic,nrf-gpiote"}
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_IDX_0 "nordic,nrf-gpiote"
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_LEN 1
#define DT_N_S_soc_S_gpiote_5000d000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/memory@20000000
 *
 * Node's generated path identifier: DT_N_S_soc_S_memory_20000000
 *
 * Binding (compatible = mmio-sram):
 *   $ZEPHYR_BASE\dts\bindings\sram\mmio-sram.yaml
 *
 * Dependency Ordinal: 27
 *
 * Requires:
 *   4   /soc
 *
 * Description:
 *   Generic on-chip SRAM description
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_memory_20000000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_20000000_EXISTS 1
#define DT_N_INST_0_mmio_sram DT_N_S_soc_S_memory_20000000
#define DT_N_NODELABEL_sram0  DT_N_S_soc_S_memory_20000000

/* Special property macros: */
#define DT_N_S_soc_S_memory_20000000_REG_NUM 1
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_ADDRESS 536870912 /* 0x20000000 */
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_SIZE 524288 /* 0x80000 */
#define DT_N_S_soc_S_memory_20000000_IRQ_NUM 0
#define DT_N_S_soc_S_memory_20000000_COMPAT_MATCHES_mmio_sram 1
#define DT_N_S_soc_S_memory_20000000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_memory_20000000_P_reg {536870912 /* 0x20000000 */, 524288 /* 0x80000 */}
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0 536870912
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1 524288
#define DT_N_S_soc_S_memory_20000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_memory_20000000_P_compatible {"mmio-sram"}
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0 "mmio-sram"
#define DT_N_S_soc_S_memory_20000000_P_compatible_LEN 1
#define DT_N_S_soc_S_memory_20000000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/spu@50003000
 *
 * Node's generated path identifier: DT_N_S_soc_S_spu_50003000
 *
 * Binding (compatible = nordic,nrf-spu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-spu.yaml
 *
 * Dependency Ordinal: 28
 *
 * Requires:
 *   4   /soc
 *   25  /soc/interrupt-controller@e000e100
 *
 * Description:
 *   Nordic SPU (System Protection Unit)
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_spu_50003000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_spu_50003000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_spu_50003000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_spu DT_N_S_soc_S_spu_50003000
#define DT_N_NODELABEL_spu         DT_N_S_soc_S_spu_50003000

/* Special property macros: */
#define DT_N_S_soc_S_spu_50003000_REG_NUM 1
#define DT_N_S_soc_S_spu_50003000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_REG_IDX_0_VAL_ADDRESS 1342189568 /* 0x50003000 */
#define DT_N_S_soc_S_spu_50003000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_spu_50003000_IRQ_NUM 1
#define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_irq 3
#define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_spu_50003000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_COMPAT_MATCHES_nordic_nrf_spu 1
#define DT_N_S_soc_S_spu_50003000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_spu_50003000_P_reg {1342189568 /* 0x50003000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_spu_50003000_P_reg_IDX_0 1342189568
#define DT_N_S_soc_S_spu_50003000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_spu_50003000_P_reg_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_interrupts {3 /* 0x3 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_0 3
#define DT_N_S_soc_S_spu_50003000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_spu_50003000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_status "okay"
#define DT_N_S_soc_S_spu_50003000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_spu_50003000_P_status_EXISTS 1
#define DT_N_S_soc_S_spu_50003000_P_compatible {"nordic,nrf-spu"}
#define DT_N_S_soc_S_spu_50003000_P_compatible_IDX_0 "nordic,nrf-spu"
#define DT_N_S_soc_S_spu_50003000_P_compatible_LEN 1
#define DT_N_S_soc_S_spu_50003000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/timer@e000e010
 *
 * Node's generated path identifier: DT_N_S_soc_S_timer_e000e010
 *
 * Dependency Ordinal: 29
 *
 * Requires:
 *   4   /soc
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_timer_e000e010_PARENT DT_N_S_soc
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_timer_e000e010_EXISTS 1
#define DT_N_INST_0_arm_armv8m_systick DT_N_S_soc_S_timer_e000e010
#define DT_N_NODELABEL_systick         DT_N_S_soc_S_timer_e000e010

/* Special property macros: */
#define DT_N_S_soc_S_timer_e000e010_REG_NUM 1
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_ADDRESS 3758153744 /* 0xe000e010 */
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_SIZE 16 /* 0x10 */
#define DT_N_S_soc_S_timer_e000e010_IRQ_NUM 0
#define DT_N_S_soc_S_timer_e000e010_COMPAT_MATCHES_arm_armv8m_systick 1
#define DT_N_S_soc_S_timer_e000e010_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_timer_e000e010_P_compatible {"arm,armv8m-systick"}
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0 "arm,armv8m-systick"
#define DT_N_S_soc_S_timer_e000e010_P_compatible_LEN 1
#define DT_N_S_soc_S_timer_e000e010_P_compatible_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_reg {3758153744 /* 0xe000e010 */, 16 /* 0x10 */}
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0 3758153744
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1 16
#define DT_N_S_soc_S_timer_e000e010_P_reg_EXISTS 1
#define DT_N_S_soc_S_timer_e000e010_P_status "disabled"
#define DT_N_S_soc_S_timer_e000e010_P_status_EXISTS 1

/*
 * Devicetree node: /soc/uicr@ff8000
 *
 * Node's generated path identifier: DT_N_S_soc_S_uicr_ff8000
 *
 * Binding (compatible = nordic,nrf-uicr):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-uicr.yaml
 *
 * Dependency Ordinal: 30
 *
 * Requires:
 *   4   /soc
 *
 * Description:
 *   Nordic UICR (User Information Configuration Registers)
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_uicr_ff8000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_uicr_ff8000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_uicr_ff8000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_uicr DT_N_S_soc_S_uicr_ff8000
#define DT_N_NODELABEL_uicr         DT_N_S_soc_S_uicr_ff8000

/* Special property macros: */
#define DT_N_S_soc_S_uicr_ff8000_REG_NUM 1
#define DT_N_S_soc_S_uicr_ff8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_REG_IDX_0_VAL_ADDRESS 16744448 /* 0xff8000 */
#define DT_N_S_soc_S_uicr_ff8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_uicr_ff8000_IRQ_NUM 0
#define DT_N_S_soc_S_uicr_ff8000_COMPAT_MATCHES_nordic_nrf_uicr 1
#define DT_N_S_soc_S_uicr_ff8000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_uicr_ff8000_P_reg {16744448 /* 0xff8000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_0 16744448
#define DT_N_S_soc_S_uicr_ff8000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_uicr_ff8000_P_reg_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_P_status "okay"
#define DT_N_S_soc_S_uicr_ff8000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_uicr_ff8000_P_status_EXISTS 1
#define DT_N_S_soc_S_uicr_ff8000_P_compatible {"nordic,nrf-uicr"}
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_IDX_0 "nordic,nrf-uicr"
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_LEN 1
#define DT_N_S_soc_S_uicr_ff8000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/crypto@50844000
 *
 * Node's generated path identifier: DT_N_S_soc_S_crypto_50844000
 *
 * Binding (compatible = nordic,nrf-cc312):
 *   $ZEPHYR_BASE\dts\bindings\crypto\nordic,nrf-cc312.yaml
 *
 * Dependency Ordinal: 31
 *
 * Requires:
 *   4   /soc
 *
 * Supports:
 *   32  /soc/crypto@50844000/crypto@50845000
 *
 * Description:
 *   Nordic Control Interface for ARM TrustZone CryptoCell 312
 */

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_crypto_50844000_PARENT DT_N_S_soc
#define DT_N_S_soc_S_crypto_50844000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_crypto_50844000_S_crypto_50845000)

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_crypto_50844000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_cc312 DT_N_S_soc_S_crypto_50844000
#define DT_N_NODELABEL_cryptocell    DT_N_S_soc_S_crypto_50844000

/* Special property macros: */
#define DT_N_S_soc_S_crypto_50844000_REG_NUM 1
#define DT_N_S_soc_S_crypto_50844000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_REG_IDX_0_VAL_ADDRESS 1350844416 /* 0x50844000 */
#define DT_N_S_soc_S_crypto_50844000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_crypto_50844000_IRQ_NUM 0
#define DT_N_S_soc_S_crypto_50844000_COMPAT_MATCHES_nordic_nrf_cc312 1
#define DT_N_S_soc_S_crypto_50844000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_crypto_50844000_P_reg {1350844416 /* 0x50844000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_0 1350844416
#define DT_N_S_soc_S_crypto_50844000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_crypto_50844000_P_reg_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_label "CRYPTOCELL"
#define DT_N_S_soc_S_crypto_50844000_P_label_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_status "okay"
#define DT_N_S_soc_S_crypto_50844000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_crypto_50844000_P_status_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_P_compatible {"nordic,nrf-cc312"}
#define DT_N_S_soc_S_crypto_50844000_P_compatible_IDX_0 "nordic,nrf-cc312"
#define DT_N_S_soc_S_crypto_50844000_P_compatible_LEN 1
#define DT_N_S_soc_S_crypto_50844000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/crypto@50844000/crypto@50845000
 *
 * Node's generated path identifier: DT_N_S_soc_S_crypto_50844000_S_crypto_50845000
 *
 * Binding (compatible = arm,cryptocell-312):
 *   $ZEPHYR_BASE\dts\bindings\crypto\arm,cryptocell-312.yaml
 *
 * Dependency Ordinal: 32
 *
 * Requires:
 *   31  /soc/crypto@50844000
 *   25  /soc/interrupt-controller@e000e100
 *
 * Description:
 *   ARM TrustZone CryptoCell 312
 */

/* Node parent (/soc/crypto@50844000) identifier: */
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_PARENT DT_N_S_soc_S_crypto_50844000
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_EXISTS 1
#define DT_N_INST_0_arm_cryptocell_312 DT_N_S_soc_S_crypto_50844000_S_crypto_50845000
#define DT_N_NODELABEL_cryptocell312   DT_N_S_soc_S_crypto_50844000_S_crypto_50845000

/* Special property macros: */
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_REG_NUM 1
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_REG_IDX_0_VAL_ADDRESS 1350848512 /* 0x50845000 */
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_IRQ_NUM 1
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_IRQ_IDX_0_VAL_irq 68
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_COMPAT_MATCHES_arm_cryptocell_312 1
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_reg {1350848512 /* 0x50845000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_reg_IDX_0 1350848512
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_reg_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_label "CRYPTOCELL312"
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_label_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_interrupts {68 /* 0x44 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_interrupts_IDX_0 68
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_compatible {"arm,cryptocell-312"}
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_compatible_IDX_0 "arm,cryptocell-312"
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_compatible_LEN 1
#define DT_N_S_soc_S_crypto_50844000_S_crypto_50845000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/adc@e000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_adc_e000
 *
 * Binding (compatible = nordic,nrf-saadc):
 *   $ZEPHYR_BASE\dts\bindings\iio\adc\nordic,nrf-saadc.yaml
 *
 * Dependency Ordinal: 33
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic Semiconductor nRF family SAADC node
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_EXISTS 1
#define DT_N_ALIAS_adc_0             DT_N_S_soc_S_peripheral_50000000_S_adc_e000
#define DT_N_INST_0_nordic_nrf_saadc DT_N_S_soc_S_peripheral_50000000_S_adc_e000
#define DT_N_NODELABEL_adc           DT_N_S_soc_S_peripheral_50000000_S_adc_e000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_IDX_0_VAL_ADDRESS 1342234624 /* 0x5000e000 */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_irq 14
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_COMPAT_MATCHES_nordic_nrf_saadc 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg {57344 /* 0xe000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_0 57344
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts {14 /* 0xe */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_0 14
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_label "ADC_0"
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible {"nordic,nrf-saadc"}
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_IDX_0 "nordic,nrf-saadc"
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_adc_e000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/clock@5000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_clock_5000
 *
 * Binding (compatible = nordic,nrf-clock):
 *   $ZEPHYR_BASE\dts\bindings\clock\nordic,nrf-clock.yaml
 *
 * Dependency Ordinal: 34
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic nRF clock control node
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_clock DT_N_S_soc_S_peripheral_50000000_S_clock_5000
#define DT_N_NODELABEL_clock         DT_N_S_soc_S_peripheral_50000000_S_clock_5000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_IDX_0_VAL_ADDRESS 1342197760 /* 0x50005000 */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_irq 5
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_COMPAT_MATCHES_nordic_nrf_clock 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_label "CLOCK"
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg {20480 /* 0x5000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_0 20480
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts {5 /* 0x5 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_0 5
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible {"nordic,nrf-clock"}
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_IDX_0 "nordic,nrf-clock"
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_clock_5000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/dppic@17000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_dppic_17000
 *
 * Binding (compatible = nordic,nrf-dppic):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-dppic.yaml
 *
 * Dependency Ordinal: 35
 *
 * Requires:
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic DPPIC (Distributed Programmable Peripheral Interconnect Controller)
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_dppic DT_N_S_soc_S_peripheral_50000000_S_dppic_17000
#define DT_N_NODELABEL_dppic         DT_N_S_soc_S_peripheral_50000000_S_dppic_17000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_IDX_0_VAL_ADDRESS 1342271488 /* 0x50017000 */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_COMPAT_MATCHES_nordic_nrf_dppic 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg {94208 /* 0x17000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_0 94208
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible {"nordic,nrf-dppic"}
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_IDX_0 "nordic,nrf-dppic"
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_label "DPPIC"
#define DT_N_S_soc_S_peripheral_50000000_S_dppic_17000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/egu@1b000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1b000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * Dependency Ordinal: 36
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic EGU (Event Generator Unit)
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_EXISTS 1
#define DT_N_ALIAS_egu_0           DT_N_S_soc_S_peripheral_50000000_S_egu_1b000
#define DT_N_INST_0_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1b000
#define DT_N_NODELABEL_egu0        DT_N_S_soc_S_peripheral_50000000_S_egu_1b000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_IDX_0_VAL_ADDRESS 1342287872 /* 0x5001b000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_irq 27
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg {110592 /* 0x1b000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_0 110592
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts {27 /* 0x1b */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_0 27
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1b000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/egu@1c000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1c000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * Dependency Ordinal: 37
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic EGU (Event Generator Unit)
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_EXISTS 1
#define DT_N_ALIAS_egu_1           DT_N_S_soc_S_peripheral_50000000_S_egu_1c000
#define DT_N_INST_1_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1c000
#define DT_N_NODELABEL_egu1        DT_N_S_soc_S_peripheral_50000000_S_egu_1c000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_IDX_0_VAL_ADDRESS 1342291968 /* 0x5001c000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_irq 28
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg {114688 /* 0x1c000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_0 114688
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts {28 /* 0x1c */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_0 28
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1c000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/egu@1d000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1d000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * Dependency Ordinal: 38
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic EGU (Event Generator Unit)
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_EXISTS 1
#define DT_N_ALIAS_egu_2           DT_N_S_soc_S_peripheral_50000000_S_egu_1d000
#define DT_N_INST_2_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1d000
#define DT_N_NODELABEL_egu2        DT_N_S_soc_S_peripheral_50000000_S_egu_1d000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_IDX_0_VAL_ADDRESS 1342296064 /* 0x5001d000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_irq 29
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg {118784 /* 0x1d000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_0 118784
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts {29 /* 0x1d */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_0 29
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1d000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/egu@1e000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1e000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * Dependency Ordinal: 39
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic EGU (Event Generator Unit)
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_EXISTS 1
#define DT_N_ALIAS_egu_3           DT_N_S_soc_S_peripheral_50000000_S_egu_1e000
#define DT_N_INST_3_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1e000
#define DT_N_NODELABEL_egu3        DT_N_S_soc_S_peripheral_50000000_S_egu_1e000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_IDX_0_VAL_ADDRESS 1342300160 /* 0x5001e000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_irq 30
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg {122880 /* 0x1e000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_0 122880
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts {30 /* 0x1e */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_0 30
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1e000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/egu@1f000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_1f000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * Dependency Ordinal: 40
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic EGU (Event Generator Unit)
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_EXISTS 1
#define DT_N_ALIAS_egu_4           DT_N_S_soc_S_peripheral_50000000_S_egu_1f000
#define DT_N_INST_4_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_1f000
#define DT_N_NODELABEL_egu4        DT_N_S_soc_S_peripheral_50000000_S_egu_1f000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_IDX_0_VAL_ADDRESS 1342304256 /* 0x5001f000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_irq 31
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg {126976 /* 0x1f000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_0 126976
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts {31 /* 0x1f */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_0 31
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_1f000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/egu@20000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_egu_20000
 *
 * Binding (compatible = nordic,nrf-egu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-egu.yaml
 *
 * Dependency Ordinal: 41
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic EGU (Event Generator Unit)
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_EXISTS 1
#define DT_N_ALIAS_egu_5           DT_N_S_soc_S_peripheral_50000000_S_egu_20000
#define DT_N_INST_5_nordic_nrf_egu DT_N_S_soc_S_peripheral_50000000_S_egu_20000
#define DT_N_NODELABEL_egu5        DT_N_S_soc_S_peripheral_50000000_S_egu_20000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_IDX_0_VAL_ADDRESS 1342308352 /* 0x50020000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_irq 32
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_COMPAT_MATCHES_nordic_nrf_egu 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg {131072 /* 0x20000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_0 131072
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts {32 /* 0x20 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_0 32
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible {"nordic,nrf-egu"}
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_IDX_0 "nordic,nrf-egu"
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_egu_20000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/gpio@842800
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_gpio_842800
 *
 * Binding (compatible = nordic,nrf-gpio):
 *   $ZEPHYR_BASE\dts\bindings\gpio\nordic,nrf-gpio.yaml
 *
 * Dependency Ordinal: 42
 *
 * Requires:
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   NRF5 GPIO node
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_EXISTS 1
#define DT_N_ALIAS_gpio_1           DT_N_S_soc_S_peripheral_50000000_S_gpio_842800
#define DT_N_INST_1_nordic_nrf_gpio DT_N_S_soc_S_peripheral_50000000_S_gpio_842800
#define DT_N_NODELABEL_gpio1        DT_N_S_soc_S_peripheral_50000000_S_gpio_842800

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_REG_IDX_0_VAL_ADDRESS 1350838272 /* 0x50842800 */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_REG_IDX_0_VAL_SIZE 768 /* 0x300 */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_COMPAT_MATCHES_nordic_nrf_gpio 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg {8660992 /* 0x842800 */, 768 /* 0x300 */}
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_IDX_0 8660992
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_IDX_1 768
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_label "GPIO_1"
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpio_controller 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_ngpios 16
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible {"nordic,nrf-gpio"}
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_IDX_0 "nordic,nrf-gpio"
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_gpio_842800_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/i2c@8000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_8000
 *
 * Dependency Ordinal: 43
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_EXISTS 1
#define DT_N_ALIAS_i2c_0    DT_N_S_soc_S_peripheral_50000000_S_i2c_8000
#define DT_N_NODELABEL_i2c0 DT_N_S_soc_S_peripheral_50000000_S_i2c_8000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_IDX_0_VAL_ADDRESS 1342210048 /* 0x50008000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_irq 8
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_0 32768
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_0 8
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_label "I2C_0"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_8000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/i2c@9000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_9000
 *
 * Binding (compatible = nordic,nrf-twim):
 *   $ZEPHYR_BASE\dts\bindings\i2c\nordic,nrf-twim.yaml
 *
 * Dependency Ordinal: 44
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic nRF family TWIM (TWI master with EasyDMA)
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_EXISTS 1
#define DT_N_ALIAS_i2c_1            DT_N_S_soc_S_peripheral_50000000_S_i2c_9000
#define DT_N_INST_0_nordic_nrf_twim DT_N_S_soc_S_peripheral_50000000_S_i2c_9000
#define DT_N_NODELABEL_i2c1         DT_N_S_soc_S_peripheral_50000000_S_i2c_9000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_IDX_0_VAL_ADDRESS 1342214144 /* 0x50009000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_irq 9
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_COMPAT_MATCHES_nordic_nrf_twim 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_0 36864
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_0 9
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_sda_pin 30
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_sda_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_scl_pin 31
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_scl_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_clock_frequency 100000
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_label "I2C_1"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible {"nordic,nrf-twim"}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_IDX_0 "nordic,nrf-twim"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_9000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/i2c@b000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_b000
 *
 * Dependency Ordinal: 45
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_EXISTS 1
#define DT_N_ALIAS_i2c_2    DT_N_S_soc_S_peripheral_50000000_S_i2c_b000
#define DT_N_NODELABEL_i2c2 DT_N_S_soc_S_peripheral_50000000_S_i2c_b000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_IDX_0_VAL_ADDRESS 1342222336 /* 0x5000b000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_irq 11
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_0 45056
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_0 11
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_label "I2C_2"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_b000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/i2c@c000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_i2c_c000
 *
 * Dependency Ordinal: 46
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_EXISTS 1
#define DT_N_ALIAS_i2c_3    DT_N_S_soc_S_peripheral_50000000_S_i2c_c000
#define DT_N_NODELABEL_i2c3 DT_N_S_soc_S_peripheral_50000000_S_i2c_c000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_REG_IDX_0_VAL_ADDRESS 1342226432 /* 0x5000c000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_VAL_irq 12
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg {49152 /* 0xc000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_IDX_0 49152
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts {12 /* 0xc */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_IDX_0 12
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_label "I2C_3"
#define DT_N_S_soc_S_peripheral_50000000_S_i2c_c000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/i2s@28000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_i2s_28000
 *
 * Binding (compatible = nordic,nrf-i2s):
 *   $ZEPHYR_BASE\dts\bindings\i2s\nordic,nrf-i2s.yaml
 *
 * Dependency Ordinal: 47
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic I2S (Inter-IC sound interface)
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_i2s DT_N_S_soc_S_peripheral_50000000_S_i2s_28000
#define DT_N_NODELABEL_i2s0        DT_N_S_soc_S_peripheral_50000000_S_i2s_28000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_IDX_0_VAL_ADDRESS 1342341120 /* 0x50028000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_irq 40
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_COMPAT_MATCHES_nordic_nrf_i2s 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg {163840 /* 0x28000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_0 163840
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts {40 /* 0x28 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_0 40
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_label "I2S_0"
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible {"nordic,nrf-i2s"}
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_IDX_0 "nordic,nrf-i2s"
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_i2s_28000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/ipc@2a000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000
 *
 * Binding (compatible = nordic,nrf-ipc):
 *   $ZEPHYR_BASE\dts\bindings\ipm\nordic,nrf-ipc.yaml
 *
 * Dependency Ordinal: 48
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic nRF family IPC (Interprocessor Communication)
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_EXISTS 1
#define DT_N_ALIAS_ipc_0           DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000
#define DT_N_INST_0_nordic_nrf_ipc DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000
#define DT_N_NODELABEL_ipc         DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_REG_IDX_0_VAL_ADDRESS 1342349312 /* 0x5002a000 */
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_IDX_0_VAL_irq 42
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_COMPAT_MATCHES_nordic_nrf_ipc 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_reg {172032 /* 0x2a000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_reg_IDX_0 172032
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_interrupts {42 /* 0x2a */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_interrupts_IDX_0 42
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible {"nordic,nrf-ipc"}
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_IDX_0 "nordic,nrf-ipc"
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_label "IPC"
#define DT_N_S_soc_S_peripheral_50000000_S_ipc_2a000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/kmu@39000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_kmu_39000
 *
 * Binding (compatible = nordic,nrf-kmu):
 *   $ZEPHYR_BASE\dts\bindings\arm\nordic,nrf-kmu.yaml
 *
 * Dependency Ordinal: 49
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic KMU (Key Management Unit)
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_kmu DT_N_S_soc_S_peripheral_50000000_S_kmu_39000
#define DT_N_NODELABEL_kmu         DT_N_S_soc_S_peripheral_50000000_S_kmu_39000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_IDX_0_VAL_ADDRESS 1342410752 /* 0x50039000 */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_irq 57
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_COMPAT_MATCHES_nordic_nrf_kmu 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg {233472 /* 0x39000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_0 233472
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts {57 /* 0x39 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_0 57
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible {"nordic,nrf-kmu"}
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_IDX_0 "nordic,nrf-kmu"
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_kmu_39000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/pdm@26000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_pdm_26000
 *
 * Binding (compatible = nordic,nrf-pdm):
 *   $ZEPHYR_BASE\dts\bindings\audio\nordic,nrf-pdm.yaml
 *
 * Dependency Ordinal: 50
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic PDM (Pulse Density Modulation interface)
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_EXISTS 1
#define DT_N_ALIAS_pdm_0           DT_N_S_soc_S_peripheral_50000000_S_pdm_26000
#define DT_N_INST_0_nordic_nrf_pdm DT_N_S_soc_S_peripheral_50000000_S_pdm_26000
#define DT_N_NODELABEL_pdm0        DT_N_S_soc_S_peripheral_50000000_S_pdm_26000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_IDX_0_VAL_ADDRESS 1342332928 /* 0x50026000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_irq 38
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_COMPAT_MATCHES_nordic_nrf_pdm 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg {155648 /* 0x26000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_0 155648
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts {38 /* 0x26 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_0 38
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible {"nordic,nrf-pdm"}
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_IDX_0 "nordic,nrf-pdm"
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_label "PDM_0"
#define DT_N_S_soc_S_peripheral_50000000_S_pdm_26000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/power@5000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_power_5000
 *
 * Binding (compatible = nordic,nrf-power):
 *   $ZEPHYR_BASE\dts\bindings\power\nordic,nrf-power.yaml
 *
 * Dependency Ordinal: 51
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic nRF power control node
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_power DT_N_S_soc_S_peripheral_50000000_S_power_5000
#define DT_N_NODELABEL_power         DT_N_S_soc_S_peripheral_50000000_S_power_5000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_IDX_0_VAL_ADDRESS 1342197760 /* 0x50005000 */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_irq 5
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_COMPAT_MATCHES_nordic_nrf_power 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg {20480 /* 0x5000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_0 20480
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts {5 /* 0x5 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_0 5
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible {"nordic,nrf-power"}
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_IDX_0 "nordic,nrf-power"
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_power_5000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/pwm@21000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_21000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-pwm.yaml
 *
 * Dependency Ordinal: 52
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   nRF PWM
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_EXISTS 1
#define DT_N_ALIAS_pwm_0           DT_N_S_soc_S_peripheral_50000000_S_pwm_21000
#define DT_N_INST_0_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_21000
#define DT_N_NODELABEL_pwm0        DT_N_S_soc_S_peripheral_50000000_S_pwm_21000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_IDX_0_VAL_ADDRESS 1342312448 /* 0x50021000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_irq 33
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg {135168 /* 0x21000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_0 135168
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_center_aligned 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_center_aligned_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_ch0_pin 28
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_ch0_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_ch0_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_ch0_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_ch1_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_ch1_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_ch2_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_ch2_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_ch3_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_ch3_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_label "PWM_0"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts {33 /* 0x21 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_0 33
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_21000_P_interrupts_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/pwm@22000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_22000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-pwm.yaml
 *
 * Dependency Ordinal: 53
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   nRF PWM
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_EXISTS 1
#define DT_N_ALIAS_pwm_1           DT_N_S_soc_S_peripheral_50000000_S_pwm_22000
#define DT_N_INST_1_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_22000
#define DT_N_NODELABEL_pwm1        DT_N_S_soc_S_peripheral_50000000_S_pwm_22000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_IDX_0_VAL_ADDRESS 1342316544 /* 0x50022000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_irq 34
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg {139264 /* 0x22000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_0 139264
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_center_aligned 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_center_aligned_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_ch0_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_ch0_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_ch1_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_ch1_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_ch2_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_ch2_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_ch3_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_ch3_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_label "PWM_1"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts {34 /* 0x22 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_0 34
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_22000_P_interrupts_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/pwm@23000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_23000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-pwm.yaml
 *
 * Dependency Ordinal: 54
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   nRF PWM
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_EXISTS 1
#define DT_N_ALIAS_pwm_2           DT_N_S_soc_S_peripheral_50000000_S_pwm_23000
#define DT_N_INST_2_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_23000
#define DT_N_NODELABEL_pwm2        DT_N_S_soc_S_peripheral_50000000_S_pwm_23000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_IDX_0_VAL_ADDRESS 1342320640 /* 0x50023000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_irq 35
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg {143360 /* 0x23000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_0 143360
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_center_aligned 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_center_aligned_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_ch0_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_ch0_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_ch1_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_ch1_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_ch2_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_ch2_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_ch3_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_ch3_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_label "PWM_2"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts {35 /* 0x23 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_0 35
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_23000_P_interrupts_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/pwm@24000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_pwm_24000
 *
 * Binding (compatible = nordic,nrf-pwm):
 *   $ZEPHYR_BASE\dts\bindings\pwm\nordic,nrf-pwm.yaml
 *
 * Dependency Ordinal: 55
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   nRF PWM
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_EXISTS 1
#define DT_N_ALIAS_pwm_3           DT_N_S_soc_S_peripheral_50000000_S_pwm_24000
#define DT_N_INST_3_nordic_nrf_pwm DT_N_S_soc_S_peripheral_50000000_S_pwm_24000
#define DT_N_NODELABEL_pwm3        DT_N_S_soc_S_peripheral_50000000_S_pwm_24000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_IDX_0_VAL_ADDRESS 1342324736 /* 0x50024000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_irq 36
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_COMPAT_MATCHES_nordic_nrf_pwm 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg {147456 /* 0x24000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_0 147456
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_center_aligned 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_center_aligned_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_ch0_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_ch0_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_ch1_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_ch1_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_ch2_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_ch2_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_ch3_inverted 0
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_ch3_inverted_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_label "PWM_3"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible {"nordic,nrf-pwm"}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_IDX_0 "nordic,nrf-pwm"
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts {36 /* 0x24 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_0 36
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_pwm_24000_P_interrupts_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/regulator@4000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_regulator_4000
 *
 * Binding (compatible = nordic,nrf-regulators):
 *   $ZEPHYR_BASE\dts\bindings\power\nordic,nrf-regulators.yaml
 *
 * Dependency Ordinal: 56
 *
 * Requires:
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic REGULATORS (voltage regulators control module)
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_regulators DT_N_S_soc_S_peripheral_50000000_S_regulator_4000
#define DT_N_NODELABEL_regulators         DT_N_S_soc_S_peripheral_50000000_S_regulator_4000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_IDX_0_VAL_ADDRESS 1342193664 /* 0x50004000 */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_COMPAT_MATCHES_nordic_nrf_regulators 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg {16384 /* 0x4000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_0 16384
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible {"nordic,nrf-regulators"}
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_IDX_0 "nordic,nrf-regulators"
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_regulator_4000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/rtc@14000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_rtc_14000
 *
 * Binding (compatible = nordic,nrf-rtc):
 *   $ZEPHYR_BASE\dts\bindings\rtc\nordic,nrf-rtc.yaml
 *
 * Dependency Ordinal: 57
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic nRF RTC (Real-Time Counter)
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_EXISTS 1
#define DT_N_ALIAS_rtc_0           DT_N_S_soc_S_peripheral_50000000_S_rtc_14000
#define DT_N_INST_0_nordic_nrf_rtc DT_N_S_soc_S_peripheral_50000000_S_rtc_14000
#define DT_N_NODELABEL_rtc0        DT_N_S_soc_S_peripheral_50000000_S_rtc_14000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_IDX_0_VAL_ADDRESS 1342259200 /* 0x50014000 */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_irq 20
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_COMPAT_MATCHES_nordic_nrf_rtc 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg {81920 /* 0x14000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_0 81920
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_ppi_wrap 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_ppi_wrap_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_fixed_top 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_fixed_top_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_clock_frequency 32768
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_label "RTC_0"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts {20 /* 0x14 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_0 20
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_prescaler 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible {"nordic,nrf-rtc"}
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_IDX_0 "nordic,nrf-rtc"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_14000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/rtc@15000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_rtc_15000
 *
 * Binding (compatible = nordic,nrf-rtc):
 *   $ZEPHYR_BASE\dts\bindings\rtc\nordic,nrf-rtc.yaml
 *
 * Dependency Ordinal: 58
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic nRF RTC (Real-Time Counter)
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_EXISTS 1
#define DT_N_ALIAS_rtc_1           DT_N_S_soc_S_peripheral_50000000_S_rtc_15000
#define DT_N_INST_1_nordic_nrf_rtc DT_N_S_soc_S_peripheral_50000000_S_rtc_15000
#define DT_N_NODELABEL_rtc1        DT_N_S_soc_S_peripheral_50000000_S_rtc_15000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_IDX_0_VAL_ADDRESS 1342263296 /* 0x50015000 */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_irq 21
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_COMPAT_MATCHES_nordic_nrf_rtc 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg {86016 /* 0x15000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_0 86016
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_ppi_wrap 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_ppi_wrap_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_fixed_top 0
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_fixed_top_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_clock_frequency 32768
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_label "RTC_1"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts {21 /* 0x15 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_0 21
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_prescaler 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible {"nordic,nrf-rtc"}
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_IDX_0 "nordic,nrf-rtc"
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_rtc_15000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/spi@8000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_8000
 *
 * Dependency Ordinal: 59
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_EXISTS 1
#define DT_N_ALIAS_spi_0    DT_N_S_soc_S_peripheral_50000000_S_spi_8000
#define DT_N_NODELABEL_spi0 DT_N_S_soc_S_peripheral_50000000_S_spi_8000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_IDX_0_VAL_ADDRESS 1342210048 /* 0x50008000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_irq 8
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_0 32768
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_0 8
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_label "SPI_0"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_8000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/spi@9000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_9000
 *
 * Dependency Ordinal: 60
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_EXISTS 1
#define DT_N_ALIAS_spi_1    DT_N_S_soc_S_peripheral_50000000_S_spi_9000
#define DT_N_NODELABEL_spi1 DT_N_S_soc_S_peripheral_50000000_S_spi_9000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_IDX_0_VAL_ADDRESS 1342214144 /* 0x50009000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_irq 9
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_0 36864
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_0 9
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_label "SPI_1"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_9000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/spi@a000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_a000
 *
 * Binding (compatible = nordic,nrf-spim):
 *   $ZEPHYR_BASE\dts\bindings\spi\nordic,nrf-spim.yaml
 *
 * Dependency Ordinal: 61
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic nRF family SPIM (SPI master with EasyDMA)
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_EXISTS 1
#define DT_N_ALIAS_spi_4            DT_N_S_soc_S_peripheral_50000000_S_spi_a000
#define DT_N_INST_1_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_a000
#define DT_N_NODELABEL_spi4         DT_N_S_soc_S_peripheral_50000000_S_spi_a000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_IDX_0_VAL_ADDRESS 1342218240 /* 0x5000a000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_irq 10
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_COMPAT_MATCHES_nordic_nrf_spim 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_miso_pull_up 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_miso_pull_up_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_miso_pull_down 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_miso_pull_down_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg {40960 /* 0xa000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_0 40960
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts {10 /* 0xa */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_0 10
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_label "SPI_4"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible {"nordic,nrf-spim"}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_IDX_0 "nordic,nrf-spim"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_a000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/spi@b000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_b000
 *
 * Binding (compatible = nordic,nrf-spim):
 *   $ZEPHYR_BASE\dts\bindings\spi\nordic,nrf-spim.yaml
 *
 * Dependency Ordinal: 62
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic nRF family SPIM (SPI master with EasyDMA)
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_EXISTS 1
#define DT_N_ALIAS_spi_2            DT_N_S_soc_S_peripheral_50000000_S_spi_b000
#define DT_N_INST_0_nordic_nrf_spim DT_N_S_soc_S_peripheral_50000000_S_spi_b000
#define DT_N_NODELABEL_spi2         DT_N_S_soc_S_peripheral_50000000_S_spi_b000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_IDX_0_VAL_ADDRESS 1342222336 /* 0x5000b000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_irq 11
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_COMPAT_MATCHES_nordic_nrf_spim 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_miso_pull_up 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_miso_pull_up_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_miso_pull_down 0
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_miso_pull_down_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_0 45056
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_0 11
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_sck_pin 32
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_sck_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_mosi_pin 32
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_mosi_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_miso_pin 36
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_miso_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_label "SPI_2"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible {"nordic,nrf-spim"}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_IDX_0 "nordic,nrf-spim"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_b000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/spi@c000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_spi_c000
 *
 * Dependency Ordinal: 63
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_EXISTS 1
#define DT_N_ALIAS_spi_3    DT_N_S_soc_S_peripheral_50000000_S_spi_c000
#define DT_N_NODELABEL_spi3 DT_N_S_soc_S_peripheral_50000000_S_spi_c000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_REG_IDX_0_VAL_ADDRESS 1342226432 /* 0x5000c000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_VAL_irq 12
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg {49152 /* 0xc000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_IDX_0 49152
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts {12 /* 0xc */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_IDX_0 12
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_label "SPI_3"
#define DT_N_S_soc_S_peripheral_50000000_S_spi_c000_P_label_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/timer@f000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_timer_f000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE\dts\bindings\timer\nordic,nrf-timer.yaml
 *
 * Dependency Ordinal: 64
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic nRF timer node
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_EXISTS 1
#define DT_N_ALIAS_timer_0           DT_N_S_soc_S_peripheral_50000000_S_timer_f000
#define DT_N_INST_0_nordic_nrf_timer DT_N_S_soc_S_peripheral_50000000_S_timer_f000
#define DT_N_NODELABEL_timer0        DT_N_S_soc_S_peripheral_50000000_S_timer_f000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_IDX_0_VAL_ADDRESS 1342238720 /* 0x5000f000 */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_irq 15
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg {61440 /* 0xf000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_0 61440
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts {15 /* 0xf */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_0 15
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_label "TIMER_0"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_prescaler 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_f000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/timer@10000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_timer_10000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE\dts\bindings\timer\nordic,nrf-timer.yaml
 *
 * Dependency Ordinal: 65
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic nRF timer node
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_EXISTS 1
#define DT_N_ALIAS_timer_1           DT_N_S_soc_S_peripheral_50000000_S_timer_10000
#define DT_N_INST_1_nordic_nrf_timer DT_N_S_soc_S_peripheral_50000000_S_timer_10000
#define DT_N_NODELABEL_timer1        DT_N_S_soc_S_peripheral_50000000_S_timer_10000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_IDX_0_VAL_ADDRESS 1342242816 /* 0x50010000 */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_irq 16
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg {65536 /* 0x10000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_0 65536
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts {16 /* 0x10 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_0 16
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_label "TIMER_1"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_prescaler 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_10000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/timer@11000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_timer_11000
 *
 * Binding (compatible = nordic,nrf-timer):
 *   $ZEPHYR_BASE\dts\bindings\timer\nordic,nrf-timer.yaml
 *
 * Dependency Ordinal: 66
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic nRF timer node
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_EXISTS 1
#define DT_N_ALIAS_timer_2           DT_N_S_soc_S_peripheral_50000000_S_timer_11000
#define DT_N_INST_2_nordic_nrf_timer DT_N_S_soc_S_peripheral_50000000_S_timer_11000
#define DT_N_NODELABEL_timer2        DT_N_S_soc_S_peripheral_50000000_S_timer_11000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_IDX_0_VAL_ADDRESS 1342246912 /* 0x50011000 */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_irq 17
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_COMPAT_MATCHES_nordic_nrf_timer 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg {69632 /* 0x11000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_0 69632
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts {17 /* 0x11 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_0 17
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_label "TIMER_2"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_prescaler 0
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible {"nordic,nrf-timer"}
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_IDX_0 "nordic,nrf-timer"
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_timer_11000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/uart@8000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_8000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
 *
 * Dependency Ordinal: 67
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic UARTE
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_EXISTS 1
#define DT_N_ALIAS_uart_0            DT_N_S_soc_S_peripheral_50000000_S_uart_8000
#define DT_N_INST_0_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_8000
#define DT_N_NODELABEL_uart0         DT_N_S_soc_S_peripheral_50000000_S_uart_8000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_IDX_0_VAL_ADDRESS 1342210048 /* 0x50008000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_irq 8
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg {32768 /* 0x8000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_0 32768
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts {8 /* 0x8 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_0 8
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_hw_flow_control 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_tx_pin 20
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_tx_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_rx_pin 22
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_rx_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_rts_pin 19
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_rts_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_cts_pin 21
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_cts_pin_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_current_speed 115200
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_label "UART_0"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_8000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/uart@9000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_9000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
 *
 * Dependency Ordinal: 68
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic UARTE
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_EXISTS 1
#define DT_N_ALIAS_uart_1            DT_N_S_soc_S_peripheral_50000000_S_uart_9000
#define DT_N_INST_1_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_9000
#define DT_N_NODELABEL_uart1         DT_N_S_soc_S_peripheral_50000000_S_uart_9000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_IDX_0_VAL_ADDRESS 1342214144 /* 0x50009000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_irq 9
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg {36864 /* 0x9000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_0 36864
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts {9 /* 0x9 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_0 9
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_hw_flow_control 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_label "UART_1"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_9000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/uart@b000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_b000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
 *
 * Dependency Ordinal: 69
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic UARTE
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_EXISTS 1
#define DT_N_ALIAS_uart_2            DT_N_S_soc_S_peripheral_50000000_S_uart_b000
#define DT_N_INST_2_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_b000
#define DT_N_NODELABEL_uart2         DT_N_S_soc_S_peripheral_50000000_S_uart_b000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_IDX_0_VAL_ADDRESS 1342222336 /* 0x5000b000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_irq 11
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg {45056 /* 0xb000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_0 45056
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts {11 /* 0xb */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_0 11
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_hw_flow_control 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_label "UART_2"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_b000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/uart@c000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_uart_c000
 *
 * Binding (compatible = nordic,nrf-uarte):
 *   $ZEPHYR_BASE\dts\bindings\serial\nordic,nrf-uarte.yaml
 *
 * Dependency Ordinal: 70
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic UARTE
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_EXISTS 1
#define DT_N_ALIAS_uart_3            DT_N_S_soc_S_peripheral_50000000_S_uart_c000
#define DT_N_INST_3_nordic_nrf_uarte DT_N_S_soc_S_peripheral_50000000_S_uart_c000
#define DT_N_NODELABEL_uart3         DT_N_S_soc_S_peripheral_50000000_S_uart_c000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_REG_IDX_0_VAL_ADDRESS 1342226432 /* 0x5000c000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_VAL_irq 12
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_COMPAT_MATCHES_nordic_nrf_uarte 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg {49152 /* 0xc000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_IDX_0 49152
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts {12 /* 0xc */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_IDX_0 12
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_hw_flow_control 0
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_label "UART_3"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible {"nordic,nrf-uarte"}
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_IDX_0 "nordic,nrf-uarte"
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_uart_c000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/vmc@81000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_vmc_81000
 *
 * Binding (compatible = nordic,nrf-vmc):
 *   $ZEPHYR_BASE\dts\bindings\power\nordic,nrf-vmc.yaml
 *
 * Dependency Ordinal: 71
 *
 * Requires:
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic VMC (Volatile Memory Controller)
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_EXISTS 1
#define DT_N_INST_0_nordic_nrf_vmc DT_N_S_soc_S_peripheral_50000000_S_vmc_81000
#define DT_N_NODELABEL_vmc         DT_N_S_soc_S_peripheral_50000000_S_vmc_81000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_REG_IDX_0_VAL_ADDRESS 1342705664 /* 0x50081000 */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_COMPAT_MATCHES_nordic_nrf_vmc 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg {528384 /* 0x81000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_IDX_0 528384
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible {"nordic,nrf-vmc"}
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_IDX_0 "nordic,nrf-vmc"
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_vmc_81000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/watchdog@18000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000
 *
 * Binding (compatible = nordic,nrf-watchdog):
 *   $ZEPHYR_BASE\dts\bindings\watchdog\nordic,nrf-watchdog.yaml
 *
 * Dependency Ordinal: 72
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic Semiconductor nRF watchdog
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_EXISTS 1
#define DT_N_ALIAS_wdt_0                DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000
#define DT_N_INST_0_nordic_nrf_watchdog DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000
#define DT_N_NODELABEL_wdt              DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000
#define DT_N_NODELABEL_wdt0             DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_IDX_0_VAL_ADDRESS 1342275584 /* 0x50018000 */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_irq 24
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_COMPAT_MATCHES_nordic_nrf_watchdog 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg {98304 /* 0x18000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_0 98304
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_label "WDT"
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts {24 /* 0x18 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_0 24
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status "okay"
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_ENUM_IDX 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible {"nordic,nrf-watchdog"}
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_IDX_0 "nordic,nrf-watchdog"
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_18000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/watchdog@19000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000
 *
 * Binding (compatible = nordic,nrf-watchdog):
 *   $ZEPHYR_BASE\dts\bindings\watchdog\nordic,nrf-watchdog.yaml
 *
 * Dependency Ordinal: 73
 *
 * Requires:
 *   25  /soc/interrupt-controller@e000e100
 *   5   /soc/peripheral@50000000
 *
 * Description:
 *   Nordic Semiconductor nRF watchdog
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_EXISTS 1
#define DT_N_INST_1_nordic_nrf_watchdog DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000
#define DT_N_NODELABEL_wdt1             DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_REG_IDX_0_VAL_ADDRESS 1342279680 /* 0x50019000 */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_VAL_irq 25
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_VAL_priority 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_COMPAT_MATCHES_nordic_nrf_watchdog 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_STATUS_disabled 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg {102400 /* 0x19000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_IDX_0 102400
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_label "WDT_1"
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts {25 /* 0x19 */, 1 /* 0x1 */}
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_IDX_0 25
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_IDX_1 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status "disabled"
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_ENUM_IDX 2
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_status_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible {"nordic,nrf-watchdog"}
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_IDX_0 "nordic,nrf-watchdog"
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_watchdog_19000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000
 *
 * Binding (compatible = nordic,nrf53-flash-controller):
 *   $ZEPHYR_BASE\dts\bindings\flash_controller\nordic,nrf53-flash-controller.yaml
 *
 * Dependency Ordinal: 74
 *
 * Requires:
 *   5   /soc/peripheral@50000000
 *
 * Supports:
 *   75  /soc/peripheral@50000000/flash-controller@39000/flash@0
 *
 * Description:
 *   Nordic NVMC (Non-Volatile Memory Controller)
 */

/* Node parent (/soc/peripheral@50000000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_PARENT DT_N_S_soc_S_peripheral_50000000
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0)

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_EXISTS 1
#define DT_N_ALIAS_flash_controller               DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000
#define DT_N_INST_0_nordic_nrf53_flash_controller DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000
#define DT_N_NODELABEL_flash_controller           DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_IDX_0_VAL_ADDRESS 1342410752 /* 0x50039000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_COMPAT_MATCHES_nordic_nrf53_flash_controller 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_label "NRF_FLASH_DRV_NAME"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg {233472 /* 0x39000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_0 233472
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_reg_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible {"nordic,nrf53-flash-controller"}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_IDX_0 "nordic,nrf53-flash-controller"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_P_compatible_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0
 *
 * Binding (compatible = soc-nv-flash):
 *   $ZEPHYR_BASE\dts\bindings\mtd\soc-nv-flash.yaml
 *
 * Dependency Ordinal: 75
 *
 * Requires:
 *   74  /soc/peripheral@50000000/flash-controller@39000
 *
 * Supports:
 *   76  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions
 *
 * Description:
 *   Flash node
 */

/* Node parent (/soc/peripheral@50000000/flash-controller@39000) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions)

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_EXISTS 1
#define DT_N_INST_0_soc_nv_flash DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0
#define DT_N_NODELABEL_flash0    DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_VAL_SIZE 1048576 /* 0x100000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_COMPAT_MATCHES_soc_nv_flash 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_STATUS_okay 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_label "NRF_FLASH"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_erase_block_size 4096
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_erase_block_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_write_block_size 4
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_write_block_size_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible {"soc-nv-flash"}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0 "soc-nv-flash"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_LEN 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg {0 /* 0x0 */, 1048576 /* 0x100000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_1 1048576
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * Dependency Ordinal: 76
 *
 * Requires:
 *   75  /soc/peripheral@50000000/flash-controller@39000/flash@0
 *
 * Supports:
 *   77  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0
 *   78  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000
 *   79  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@40000
 *   80  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@80000
 *   81  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@b0000
 *   82  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f0000
 *   83  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@fa000
 *
 * Description:
 *   Flash partitions parent node
 */

/* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000) fn(DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000)

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_EXISTS 1
#define DT_N_INST_0_fixed_partitions DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_REG_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_COMPAT_MATCHES_fixed_partitions 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_STATUS_okay 1

/* (No generic property macros) */

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@0
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * Dependency Ordinal: 77
 *
 * Requires:
 *   76  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions
 *
 * Description:
 *   Flash partition child node
 */

/* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_EXISTS 1
#define DT_N_NODELABEL_boot_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 65536 /* 0x10000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_STATUS_okay 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PARTITION_ID 0

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label "mcuboot"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_read_only 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg {0 /* 0x0 */, 65536 /* 0x10000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1 65536
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@10000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * Dependency Ordinal: 78
 *
 * Requires:
 *   76  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions
 *
 * Description:
 *   Flash partition child node
 */

/* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_EXISTS 1
#define DT_N_NODELABEL_slot0_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_ADDRESS 65536 /* 0x10000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_SIZE 196608 /* 0x30000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_STATUS_okay 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PARTITION_ID 1

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label "image-0"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_read_only 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg {65536 /* 0x10000 */, 196608 /* 0x30000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0 65536
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1 196608
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@40000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * Dependency Ordinal: 79
 *
 * Requires:
 *   76  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions
 *
 * Description:
 *   Flash partition child node
 */

/* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000_EXISTS 1
#define DT_N_NODELABEL_slot0_ns_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000_REG_IDX_0_VAL_ADDRESS 262144 /* 0x40000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000_STATUS_okay 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000_PARTITION_ID 2

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000_P_label "image-0-nonsecure"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000_P_read_only 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000_P_reg {262144 /* 0x40000 */, 262144 /* 0x40000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000_P_reg_IDX_0 262144
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000_P_reg_IDX_1 262144
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@80000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * Dependency Ordinal: 80
 *
 * Requires:
 *   76  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions
 *
 * Description:
 *   Flash partition child node
 */

/* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_EXISTS 1
#define DT_N_NODELABEL_slot1_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_VAL_ADDRESS 524288 /* 0x80000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_VAL_SIZE 196608 /* 0x30000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_STATUS_okay 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PARTITION_ID 3

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label "image-1"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_read_only 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg {524288 /* 0x80000 */, 196608 /* 0x30000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_0 524288
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_1 196608
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@b0000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * Dependency Ordinal: 81
 *
 * Requires:
 *   76  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions
 *
 * Description:
 *   Flash partition child node
 */

/* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000_EXISTS 1
#define DT_N_NODELABEL_slot1_ns_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000_REG_IDX_0_VAL_ADDRESS 720896 /* 0xb0000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000_STATUS_okay 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000_PARTITION_ID 4

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000_P_label "image-1-nonsecure"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000_P_read_only 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000_P_reg {720896 /* 0xb0000 */, 262144 /* 0x40000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000_P_reg_IDX_0 720896
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000_P_reg_IDX_1 262144
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@f0000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * Dependency Ordinal: 82
 *
 * Requires:
 *   76  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions
 *
 * Description:
 *   Flash partition child node
 */

/* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_EXISTS 1
#define DT_N_NODELABEL_scratch_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_VAL_ADDRESS 983040 /* 0xf0000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_VAL_SIZE 40960 /* 0xa000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_STATUS_okay 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PARTITION_ID 5

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label "image-scratch"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_read_only 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg {983040 /* 0xf0000 */, 40960 /* 0xa000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_0 983040
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_1 40960
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions/partition@fa000
 *
 * Node's generated path identifier: DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE\dts\bindings\mtd\partition.yaml
 *
 * Dependency Ordinal: 83
 *
 * Requires:
 *   76  /soc/peripheral@50000000/flash-controller@39000/flash@0/partitions
 *
 * Description:
 *   Flash partition child node
 */

/* Node parent (/soc/peripheral@50000000/flash-controller@39000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PARENT DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD(fn) 

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_EXISTS 1
#define DT_N_NODELABEL_storage_partition DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000

/* Special property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_NUM 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_VAL_ADDRESS 1024000 /* 0xfa000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_VAL_SIZE 24576 /* 0x6000 */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_IRQ_NUM 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_STATUS_okay 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PARTITION_ID 6

/* Generic property macros: */
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label "storage"
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_read_only 0
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg {1024000 /* 0xfa000 */, 24576 /* 0x6000 */}
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_0 1024000
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_1 24576
#define DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_EXISTS 1

/*
 * Chosen nodes
 */
#define DT_CHOSEN_zephyr_flash_controller                 DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000
#define DT_CHOSEN_zephyr_flash_controller_EXISTS          1
#define DT_CHOSEN_zephyr_console                          DT_N_S_soc_S_peripheral_50000000_S_uart_8000
#define DT_CHOSEN_zephyr_console_EXISTS                   1
#define DT_CHOSEN_zephyr_shell_uart                       DT_N_S_soc_S_peripheral_50000000_S_uart_8000
#define DT_CHOSEN_zephyr_shell_uart_EXISTS                1
#define DT_CHOSEN_zephyr_uart_mcumgr                      DT_N_S_soc_S_peripheral_50000000_S_uart_8000
#define DT_CHOSEN_zephyr_uart_mcumgr_EXISTS               1
#define DT_CHOSEN_zephyr_bt_mon_uart                      DT_N_S_soc_S_peripheral_50000000_S_uart_8000
#define DT_CHOSEN_zephyr_bt_mon_uart_EXISTS               1
#define DT_CHOSEN_zephyr_bt_c2h_uart                      DT_N_S_soc_S_peripheral_50000000_S_uart_8000
#define DT_CHOSEN_zephyr_bt_c2h_uart_EXISTS               1
#define DT_CHOSEN_zephyr_ipc_shm                          DT_N_S_reserved_memory_S_memory_20070000
#define DT_CHOSEN_zephyr_ipc_shm_EXISTS                   1
#define DT_CHOSEN_zephyr_sram                             DT_N_S_reserved_memory_S_image_20000000
#define DT_CHOSEN_zephyr_sram_EXISTS                      1
#define DT_CHOSEN_zephyr_flash                            DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0
#define DT_CHOSEN_zephyr_flash_EXISTS                     1
#define DT_CHOSEN_zephyr_code_partition                   DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000
#define DT_CHOSEN_zephyr_code_partition_EXISTS            1
#define DT_CHOSEN_zephyr_sram_secure_partition            DT_N_S_reserved_memory_S_image_s_20000000
#define DT_CHOSEN_zephyr_sram_secure_partition_EXISTS     1
#define DT_CHOSEN_zephyr_sram_non_secure_partition        DT_N_S_reserved_memory_S_image_ns_20010000
#define DT_CHOSEN_zephyr_sram_non_secure_partition_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_0 DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000
#define DT_COMPAT_fixed_partitions_LABEL_image_0_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_0_nonsecure DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_40000
#define DT_COMPAT_fixed_partitions_LABEL_image_0_nonsecure_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_1 DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000
#define DT_COMPAT_fixed_partitions_LABEL_image_1_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_1_nonsecure DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_b0000
#define DT_COMPAT_fixed_partitions_LABEL_image_1_nonsecure_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_scratch DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000
#define DT_COMPAT_fixed_partitions_LABEL_image_scratch_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_storage DT_N_S_soc_S_peripheral_50000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000
#define DT_COMPAT_fixed_partitions_LABEL_storage_EXISTS 1

/*
 * Macros for compatibles with status "okay" nodes
 */
#define DT_COMPAT_HAS_OKAY_nordic_nrf5340_pdk_nrf5340_cpuapp 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf5340_cpuapp_qkaa 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf5340_cpuapp 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf5340_cpu0_qkaa 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf5340_cpu0 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf53 1
#define DT_COMPAT_HAS_OKAY_simple_bus 1
#define DT_COMPAT_HAS_OKAY_arm_v8m_nvic 1
#define DT_COMPAT_HAS_OKAY_mmio_sram 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf53_flash_controller 1
#define DT_COMPAT_HAS_OKAY_soc_nv_flash 1
#define DT_COMPAT_HAS_OKAY_fixed_partitions 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_saadc 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_dppic 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_egu 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_ipc 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_kmu 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_regulators 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_vmc 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_uarte 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_twim 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_spim 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_pwm 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_gpio 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_rtc 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_clock 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_power 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_watchdog 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_timer 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_cc312 1
#define DT_COMPAT_HAS_OKAY_arm_cryptocell_312 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_gpiote 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_spu 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_ficr 1
#define DT_COMPAT_HAS_OKAY_nordic_nrf_uicr 1
#define DT_COMPAT_HAS_OKAY_arm_cortex_m33f 1
#define DT_COMPAT_HAS_OKAY_arm_armv8m_mpu 1
#define DT_COMPAT_HAS_OKAY_gpio_leds 1
#define DT_COMPAT_HAS_OKAY_gpio_keys 1

/*
 * Macros for status "okay" instances of each compatible
 */
#define DT_N_INST_nordic_nrf5340_pdk_nrf5340_cpuapp_NUM_OKAY 1
#define DT_N_INST_nordic_nrf5340_cpuapp_qkaa_NUM_OKAY 1
#define DT_N_INST_nordic_nrf5340_cpuapp_NUM_OKAY 1
#define DT_N_INST_nordic_nrf5340_cpu0_qkaa_NUM_OKAY 1
#define DT_N_INST_nordic_nrf5340_cpu0_NUM_OKAY 1
#define DT_N_INST_nordic_nrf53_NUM_OKAY 1
#define DT_N_INST_simple_bus_NUM_OKAY 1
#define DT_N_INST_arm_v8m_nvic_NUM_OKAY 1
#define DT_N_INST_mmio_sram_NUM_OKAY 1
#define DT_N_INST_nordic_nrf53_flash_controller_NUM_OKAY 1
#define DT_N_INST_soc_nv_flash_NUM_OKAY 1
#define DT_N_INST_fixed_partitions_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_saadc_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_dppic_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_egu_NUM_OKAY 6
#define DT_N_INST_nordic_nrf_ipc_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_kmu_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_regulators_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_vmc_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_uarte_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_twim_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_spim_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_pwm_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_gpio_NUM_OKAY 2
#define DT_N_INST_nordic_nrf_rtc_NUM_OKAY 2
#define DT_N_INST_nordic_nrf_clock_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_power_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_watchdog_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_timer_NUM_OKAY 3
#define DT_N_INST_nordic_nrf_cc312_NUM_OKAY 1
#define DT_N_INST_arm_cryptocell_312_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_gpiote_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_spu_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_ficr_NUM_OKAY 1
#define DT_N_INST_nordic_nrf_uicr_NUM_OKAY 1
#define DT_N_INST_arm_cortex_m33f_NUM_OKAY 1
#define DT_N_INST_arm_armv8m_mpu_NUM_OKAY 1
#define DT_N_INST_gpio_leds_NUM_OKAY 1
#define DT_N_INST_gpio_keys_NUM_OKAY 1
#define DT_FOREACH_OKAY_INST_nordic_nrf5340_pdk_nrf5340_cpuapp(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf5340_cpuapp_qkaa(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf5340_cpuapp(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf5340_cpu0_qkaa(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf5340_cpu0(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf53(fn) fn(0)
#define DT_FOREACH_OKAY_INST_simple_bus(fn) fn(0)
#define DT_FOREACH_OKAY_INST_arm_v8m_nvic(fn) fn(0)
#define DT_FOREACH_OKAY_INST_mmio_sram(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf53_flash_controller(fn) fn(0)
#define DT_FOREACH_OKAY_INST_soc_nv_flash(fn) fn(0)
#define DT_FOREACH_OKAY_INST_fixed_partitions(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_saadc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_dppic(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_egu(fn) fn(0) fn(1) fn(2) fn(3) fn(4) fn(5)
#define DT_FOREACH_OKAY_INST_nordic_nrf_ipc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_kmu(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_regulators(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_vmc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_uarte(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_twim(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_spim(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_pwm(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_gpio(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_nordic_nrf_rtc(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_nordic_nrf_clock(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_power(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_watchdog(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_timer(fn) fn(0) fn(1) fn(2)
#define DT_FOREACH_OKAY_INST_nordic_nrf_cc312(fn) fn(0)
#define DT_FOREACH_OKAY_INST_arm_cryptocell_312(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_gpiote(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_spu(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_ficr(fn) fn(0)
#define DT_FOREACH_OKAY_INST_nordic_nrf_uicr(fn) fn(0)
#define DT_FOREACH_OKAY_INST_arm_cortex_m33f(fn) fn(0)
#define DT_FOREACH_OKAY_INST_arm_armv8m_mpu(fn) fn(0)
#define DT_FOREACH_OKAY_INST_gpio_leds(fn) fn(0)
#define DT_FOREACH_OKAY_INST_gpio_keys(fn) fn(0)

/*
 * Bus information for status "okay" nodes of each compatible
 */
