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Zephyr nrf5340 cpu app SPI1 burst read missing byte

Hi,

I am trying to burst read FIFO of ADXL362 with zephyr adxl362 sample. 1 byte tx (read fifo command) and n byte rx ( reading the fifo data);

Zephyr is the last version 3.0 , ncs is 1.9.1   , mcu is nrf5340 app s

i write this function to set a spi transaction is like this ; 

adxl362.c

#define ADXL362_READ_FIFO          0x0D
int adxl362ext_get_fifo_data(const struct device *dev,uint8_t *read_buf, uint8_t count)
{
	const struct adxl362ext_config *cfg = dev->config;
	uint8_t access[1] = { ADXL362_READ_FIFO};
volatile int i=1,m=9;
	const struct spi_buf txbuf =
	{
			.buf = access,
			.len = 1
	};

	const struct spi_buf_set tx = {
		.buffers = &txbuf,
		.count = 1
	};	

	const struct spi_buf rxbuf =	{
			.buf = read_buf,
			.len = count
	};

	const struct spi_buf_set rx = {
		.buffers = &rxbuf,
		.count = 1
	};

	return spi_transceive_dt(&cfg->bus, &tx, &rx);
}

i call it from the standard function comes with the adxl362 sample ; 

adxl362_trigger.c

uint8_t Acc_Data[400];

static void adxl362_thread_cb(const struct device *dev)
{
	struct adxl362_data *drv_data = dev->data;
	uint8_t status_buf;

	/* Clears activity and inactivity interrupt */
	if (adxl362_get_status(dev, &status_buf)) {
		LOG_ERR("Unable to get status.");
		return;
	}

	k_mutex_lock(&drv_data->trigger_mutex, K_FOREVER);
	if (drv_data->th_handler != NULL) {
		if (ADXL362_STATUS_CHECK_INACT(status_buf) ||
		    ADXL362_STATUS_CHECK_ACTIVITY(status_buf)) {
			drv_data->th_handler(dev, &drv_data->th_trigger);
		}
	}

	if (drv_data->drdy_handler != NULL &&
	    ADXL362_STATUS_CHECK_DATA_READY(status_buf)) {
		drv_data->drdy_handler(dev, &drv_data->drdy_trigger);
	}

	
	adxl362ext_get_fifo_data(dev,(uint8_t *)&Acc_Data,7);

	k_mutex_unlock(&drv_data->trigger_mutex);
}

Result is like this ; 
Debug:

I can also verify by logic analyzer 1 byte is missing from the original count. 

If i set it to 1 , i can not see any spi clocks for rx buffer.

If i set it to 6 , i can see that spi will be clocked out for 5 bytes.

I couldn't locate the code makes it from 7 to 6, or 6 to 5  or n  to n-1 .

Thanks

  • I think you understand what is occuring now, so I don't think there is anything I can add, but just to clarify a bit on how it works:

    In SPI there is a clock signal that synchronously output/input the MOSI (from tx_buf)/MISO(to rx_buf) signals, this is done in parallel by hardware. It should always have been this, though it might have been small changes whether the entire transaction was handled in one transfer and/or on byte level depending on the software/hardware implementation. Depending on the driver/library it might have been that the above described low level buffering was masked out on higher abstraction layers (e.g. that you didn't observe that the low level hardware buffer was +1 byte).

    Best regards,
    Kenneth

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