<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://test-devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>how to set the High-drive QSPI?</title><link>https://test-devzone.nordicsemi.com/f/nordic-q-a/87987/how-to-set-the-high-drive-qspi</link><description>how to set the High-drive QSPI? 
 NRF_GPIO_PIN_H0H1 
 
 nrf_gpio_cfg ( mosi_pin ,
 NRF_GPIO_PIN_DIR_OUTPUT ,
 NRF_GPIO_PIN_INPUT_CONNECT ,
 NRF_GPIO_PIN_NOPULL ,
 NRF_GPIO_PIN_H0H1 ,
 NRF_GPIO_PIN_NOSENSE ) ;</description><dc:language>en-US</dc:language><generator>Telligent Community 13 Non-Production</generator><lastBuildDate>Mon, 23 May 2022 12:14:38 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://test-devzone.nordicsemi.com/f/nordic-q-a/87987/how-to-set-the-high-drive-qspi" /><item><title>RE: how to set the High-drive QSPI?</title><link>https://test-devzone.nordicsemi.com/thread/369015?ContentTypeID=1</link><pubDate>Mon, 23 May 2022 12:14:38 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:f2bf4799-b1f6-47fe-8100-ba5d11bff728</guid><dc:creator>user75734</dc:creator><description>&lt;p&gt;Hi&lt;/p&gt;
&lt;p&gt;Yes, all pins should be set to &amp;quot;high drive&amp;quot; to ensure the QSPI altogether runs in high drive. It&amp;#39;s described in detail what to do in &lt;a href="https://infocenter.nordicsemi.com/index.jsp?topic=%2Fps_nrf52840%2Fqspi.html&amp;amp;anchor=configuration2"&gt;the product specification of the nRF52840&lt;/a&gt;.&lt;/p&gt;
&lt;p&gt;Best regards,&lt;/p&gt;
&lt;p&gt;Simon&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: how to set the High-drive QSPI?</title><link>https://test-devzone.nordicsemi.com/thread/368904?ContentTypeID=1</link><pubDate>Mon, 23 May 2022 01:54:14 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:40fd2a69-c5ad-4277-817e-8b0cf5d4c77c</guid><dc:creator>user89602</dc:creator><description>&lt;p&gt;1.init qspi&lt;/p&gt;
&lt;p&gt;2.set all pin&amp;nbsp;&amp;nbsp;&lt;span&gt;NRF_GPIO_PIN_H0H1&amp;nbsp;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Is it the right way to set up the&amp;nbsp; QSPI Hight-drive?&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: how to set the High-drive QSPI?</title><link>https://test-devzone.nordicsemi.com/thread/368736?ContentTypeID=1</link><pubDate>Fri, 20 May 2022 08:06:34 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:722dc86d-381a-45b1-abcd-8f5c01a629d0</guid><dc:creator>user75734</dc:creator><description>&lt;p&gt;Hi&lt;/p&gt;
&lt;p&gt;Is this setup working for you, or are you still having trouble? Let me know if this case can be closed.&lt;/p&gt;
&lt;p&gt;Best regards,&lt;/p&gt;
&lt;p&gt;Simon&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: how to set the High-drive QSPI?</title><link>https://test-devzone.nordicsemi.com/thread/368500?ContentTypeID=1</link><pubDate>Thu, 19 May 2022 06:09:27 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:f383ec8c-1b4e-4e68-8bb3-954e1ddb0bdd</guid><dc:creator>user89602</dc:creator><description>&lt;p&gt;SDK15.2&lt;/p&gt;
&lt;p&gt;1.init qspi&lt;/p&gt;
&lt;p&gt;2.set all pin&amp;nbsp;&amp;nbsp;&lt;span&gt;NRF_GPIO_PIN_H0H1&amp;nbsp;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;/span&gt;&lt;/p&gt;
&lt;div style="background-color:#1e1e1e;color:#abb2bf;font-family:&amp;#39;Consolas&amp;#39;;font-size:13.0pt;font-style:normal;font-weight:normal;text-decoration:none;"&gt;
&lt;pre&gt; &lt;span&gt;nrf_drv_qspi_config_t&lt;/span&gt; &lt;span&gt;config&lt;/span&gt;&lt;span&gt;;&lt;/span&gt;
        &lt;span&gt;config&lt;/span&gt;.&lt;span&gt;pins&lt;/span&gt;.&lt;span&gt;csn_pin&lt;/span&gt; &lt;span&gt;=&lt;/span&gt; &lt;span&gt;FLASH_QSPI_CSN_NUMBER&lt;/span&gt;&lt;span&gt;;&lt;/span&gt;
        &lt;span&gt;config&lt;/span&gt;.&lt;span&gt;pins&lt;/span&gt;.&lt;span&gt;sck_pin&lt;/span&gt; &lt;span&gt;=&lt;/span&gt; &lt;span&gt;FLASH_QSPI_SCK_NUMBER&lt;/span&gt;&lt;span&gt;;&lt;/span&gt;
        &lt;span&gt;config&lt;/span&gt;.&lt;span&gt;pins&lt;/span&gt;.&lt;span&gt;io0_pin&lt;/span&gt; &lt;span&gt;=&lt;/span&gt; &lt;span&gt;FLASH_QSPI_IO0_NUMBER&lt;/span&gt;&lt;span&gt;;&lt;/span&gt;
        &lt;span&gt;config&lt;/span&gt;.&lt;span&gt;pins&lt;/span&gt;.&lt;span&gt;io1_pin&lt;/span&gt; &lt;span&gt;=&lt;/span&gt; &lt;span&gt;FLASH_QSPI_IO1_NUMBER&lt;/span&gt;&lt;span&gt;;&lt;/span&gt;
        &lt;span&gt;config&lt;/span&gt;.&lt;span&gt;pins&lt;/span&gt;.&lt;span&gt;io2_pin&lt;/span&gt; &lt;span&gt;=&lt;/span&gt; &lt;span&gt;FLASH_QSPI_IO2_NUMBER&lt;/span&gt;&lt;span&gt;;&lt;/span&gt;
        &lt;span&gt;config&lt;/span&gt;.&lt;span&gt;pins&lt;/span&gt;.&lt;span&gt;io3_pin&lt;/span&gt; &lt;span&gt;=&lt;/span&gt; &lt;span&gt;FLASH_QSPI_IO3_NUMBER&lt;/span&gt;&lt;span&gt;;&lt;/span&gt;


        &lt;span&gt;config&lt;/span&gt;.&lt;span&gt;prot_if&lt;/span&gt;.&lt;span&gt;readoc&lt;/span&gt; &lt;span&gt;=&lt;/span&gt; &lt;span&gt;NRF_QSPI_READOC_READ4O&lt;/span&gt;&lt;span&gt;;&lt;/span&gt;
        &lt;span&gt;config&lt;/span&gt;.&lt;span&gt;prot_if&lt;/span&gt;.&lt;span&gt;writeoc&lt;/span&gt; &lt;span&gt;=&lt;/span&gt; &lt;span&gt;NRF_QSPI_WRITEOC_PP4O&lt;/span&gt;&lt;span&gt;;&lt;/span&gt;
        &lt;span&gt;config&lt;/span&gt;.&lt;span&gt;prot_if&lt;/span&gt;.&lt;span&gt;addrmode&lt;/span&gt; &lt;span&gt;=&lt;/span&gt; &lt;span&gt;NRF_QSPI_ADDRMODE_24BIT&lt;/span&gt;&lt;span&gt;;&lt;/span&gt;
        &lt;span&gt;config&lt;/span&gt;.&lt;span&gt;prot_if&lt;/span&gt;.&lt;span&gt;dpmconfig&lt;/span&gt; &lt;span&gt;=&lt;/span&gt; &lt;span&gt;0&lt;/span&gt;&lt;span&gt;;&lt;/span&gt;
        &lt;span&gt;config&lt;/span&gt;.&lt;span&gt;phy_if&lt;/span&gt;.&lt;span&gt;sck_delay&lt;/span&gt; &lt;span&gt;=&lt;/span&gt; &lt;span&gt;0x01&lt;/span&gt;&lt;span&gt;;&lt;/span&gt;
        &lt;span&gt;config&lt;/span&gt;.&lt;span&gt;phy_if&lt;/span&gt;.&lt;span&gt;dpmen&lt;/span&gt; &lt;span&gt;=&lt;/span&gt; &lt;span&gt;0&lt;/span&gt;&lt;span&gt;;&lt;/span&gt;
        &lt;span&gt;config&lt;/span&gt;.&lt;span&gt;phy_if&lt;/span&gt;.&lt;span&gt;spi_mode&lt;/span&gt; &lt;span&gt;=&lt;/span&gt; &lt;span&gt;NRF_QSPI_MODE_0&lt;/span&gt;&lt;span&gt;;&lt;/span&gt;
        &lt;span&gt;config&lt;/span&gt;.&lt;span&gt;phy_if&lt;/span&gt;.&lt;span&gt;sck_freq&lt;/span&gt; &lt;span&gt;=&lt;/span&gt; &lt;span&gt;FLASH_QSPI_HZ&lt;/span&gt;&lt;span&gt;;&lt;/span&gt;
        &lt;span&gt;config&lt;/span&gt;.&lt;span&gt;irq_priority&lt;/span&gt; &lt;span&gt;=&lt;/span&gt; &lt;span&gt;0x06&lt;/span&gt;&lt;span&gt;;&lt;/span&gt;
        &lt;span&gt;config&lt;/span&gt;.&lt;span&gt;xip_offset&lt;/span&gt; &lt;span&gt;=&lt;/span&gt; &lt;span&gt;0&lt;/span&gt;&lt;span&gt;;&lt;/span&gt;
        &lt;span&gt;int&lt;/span&gt; &lt;span&gt;err_code&lt;/span&gt; &lt;span&gt;=&lt;/span&gt; &lt;span&gt;nrf_drv_qspi_init&lt;/span&gt;(&lt;span&gt;&amp;amp;&lt;/span&gt;&lt;span&gt;config&lt;/span&gt;, &lt;span&gt;NULL&lt;/span&gt;, &lt;span&gt;NULL&lt;/span&gt;)&lt;span&gt;;&lt;/span&gt;
        &lt;span&gt;APP_ERROR_CHECK&lt;/span&gt;(&lt;span&gt;err_code&lt;/span&gt;)&lt;span&gt;;&lt;/span&gt;




        &lt;span&gt;nrf_gpio_cfg&lt;/span&gt;(&lt;span&gt;FLASH_QSPI_CSN_NUMBER&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_DIR_OUTPUT&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_INPUT_CONNECT&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_NOPULL&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_H0H1&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_NOSENSE&lt;/span&gt;)&lt;span&gt;;&lt;/span&gt;

        &lt;span&gt;nrf_gpio_cfg&lt;/span&gt;(&lt;span&gt;FLASH_QSPI_SCK_NUMBER&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_DIR_OUTPUT&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_INPUT_CONNECT&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_NOPULL&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_H0H1&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_NOSENSE&lt;/span&gt;)&lt;span&gt;;&lt;/span&gt;

        &lt;span&gt;nrf_gpio_cfg&lt;/span&gt;(&lt;span&gt;FLASH_QSPI_IO1_NUMBER&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_DIR_OUTPUT&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_INPUT_CONNECT&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_NOPULL&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_H0H1&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_NOSENSE&lt;/span&gt;)&lt;span&gt;;&lt;/span&gt;

        &lt;span&gt;nrf_gpio_cfg&lt;/span&gt;(&lt;span&gt;FLASH_QSPI_IO2_NUMBER&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_DIR_OUTPUT&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_INPUT_CONNECT&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_NOPULL&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_H0H1&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_NOSENSE&lt;/span&gt;)&lt;span&gt;;&lt;/span&gt;

        &lt;span&gt;nrf_gpio_cfg&lt;/span&gt;(&lt;span&gt;FLASH_QSPI_IO3_NUMBER&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_DIR_OUTPUT&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_INPUT_CONNECT&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_NOPULL&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_H0H1&lt;/span&gt;,
                     &lt;span&gt;NRF_GPIO_PIN_NOSENSE&lt;/span&gt;)&lt;span&gt;;&lt;br /&gt;&lt;br /&gt;&lt;/span&gt;&lt;/pre&gt;
&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: how to set the High-drive QSPI?</title><link>https://test-devzone.nordicsemi.com/thread/368324?ContentTypeID=1</link><pubDate>Wed, 18 May 2022 11:56:09 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:2f59a5fd-f6e3-49a2-bd62-62145fc3d770</guid><dc:creator>user75734</dc:creator><description>&lt;p&gt;Hi&lt;/p&gt;
&lt;p&gt;What SDK and SDK version are you using for development? You can see how to set the drive strength for any GPIO in &lt;a href="https://test-devzone.nordicsemi.com/f/nordic-q-a/81543/how-can-gpio-pins-be-set-to-high-drive"&gt;this case &lt;/a&gt;where my colleague Amanda explains how to.&lt;/p&gt;
&lt;p&gt;Best regards,&lt;/p&gt;
&lt;p&gt;Simon&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>