Interrupt Missing In When QSPI Is Configured In Interrupt Mode

RE: Interrupt Missing In When QSPI Is Configured In Interrupt Mode

user111786 — Tue, 14 Jun 2022 11:08:15 GMT

Hi,

As previously said, length must be multiple of 4 bytes. Even though you can write more bytes (not multiple of 4), you should be aware that it is against the product specification.

Best regards,
Dejan

RE: Interrupt Missing In When QSPI Is Configured In Interrupt Mode

user89683 — Mon, 13 Jun 2022 10:33:07 GMT

Hello Dejans,

As mentioned in the previous answer writing non-aligned words(WRITE:CNT having non multiple of 4) are also successful.
We are observing this issue only when the WRITE:CNT is lesser than 4

Thanks,
Sakib

RE: Interrupt Missing In When QSPI Is Configured In Interrupt Mode

user111786 — Mon, 13 Jun 2022 08:42:02 GMT

Hi,

WRITE.CNT is transfer length in bytes. The length must be multiple of 4 bytes.

Best regards,
Dejan

RE: Interrupt Missing In When QSPI Is Configured In Interrupt Mode

user89683 — Mon, 13 Jun 2022 06:36:17 GMT

Hello Dejans,

Thank you for the information, Following are our observation while debugging the issue

The interrupt is never generated if the number of bytes to be written is lesser than 4 (i.e 1, 2, 3)
i.e In the "p_reg->WRITE.CNT = length" the length is lesser than 4

Please note that the write is successful for all the values greater than equal to 4.

Please let us know if this is the expected working of the QSPI driver?

Thanks,
Sakib

RE: Interrupt Missing In When QSPI Is Configured In Interrupt Mode

user111786 — Wed, 08 Jun 2022 16:33:01 GMT

Hi,

With regard to your question about interrupts not being generated, SoftDevice determines interrupt priority levels in such way that most critical interrupts have lowest possible interrupt levels.
In the same link you can read that it is expected for interrupts to be postponed or preemted which can lead to a longer perceived interrupt latency and execution time.

Best regards,
Dejan

RE: Interrupt Missing In When QSPI Is Configured In Interrupt Mode

user89683 — Tue, 07 Jun 2022 16:17:37 GMT

Hello Dejans,

We are using SDK V15.3.0, softdevice S140(In disabled state)

Following are more details on the active peripherals, their functions and priority levels while the PSRAM read/write action is performed

1. General purpose timer Instance 1 running at frequency of 1Khz with priority level at 6
2. RTC timer sampling 5 channel enabled internal SAADC at frequency of 1Khz with both the SAADC and RTC priority levels at 6
3. UART at the baud rate of 115200 with priority level at 6
4. Application timers with priority level at 6
5. SPI interfaced external ADC collecting sensor data using PPI 100kSamples/Sec, the SPI priority level at 2
6. QSPI at priority level 6

Referring to our PsramRead and PsramWrite functions, the control waits in the while loop until the interrupt indicates free state of the QSPI for a maximum of 10sec(the WatchDog triggers after 10 sec)
We believe that the interrupts in the cortex M4 controllers may occur in a delayed form if configured at a lower priority but never be missed, please let us know if this understanding is valid for the issue that we are facing?

Thanks and Regards,
Sakib

RE: Interrupt Missing In When QSPI Is Configured In Interrupt Mode

user111786 — Tue, 07 Jun 2022 13:13:12 GMT

Hi,

Which SDK and version do you use?

If you use nRF5, you can take a look at qspi in the documentation. You could also take a look at the sample in \examples\peripheral\qspi.
You could try changing interrupt priority value. More information about interrupt priorities is available in this discussion.

Best regards,
Dejan