Instruction and Data Fault registers

RE: Instruction and Data Fault registers

user86158 — Mon, 13 Jun 2022 14:16:47 GMT

Hi Ovrebekk

Thanks for the feedback, and yes indeed it is the R4 (and not the M3) as you rightly indicated.

I will mark my question as answered.

Cheers

RMV

RE: Instruction and Data Fault registers

user2116 — Mon, 13 Jun 2022 10:50:27 GMT

Hi RMW

I found a reference to these registers in the Cortex R4, but I don't think there are any such registers in the M4.

I would recommend using the HardFault handling library in the nRF5 SDK, then you will get information about the source of errors.

Best regards
Torbjørn

RE: Instruction and Data Fault registers

user86158 — Fri, 10 Jun 2022 20:10:39 GMT

Just an update..

I was able to narrow down the root cause of the failure -- through some random trial and error -- that the issue was because I was using two asynchronous and independent schedulers that were completely disconnected and that led to invalid states in my application later on.

However, I would still like to understand how I can narrow down the offending instruction that triggered an instruction fetch/decode error or a precise/imprecise data access error.

Cheers

RMV