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VDD and VDD_GPIO at 3V

user105759

Hi there,

the nrf9160 DK user guide seems to recommend that VDD should be 1.8V and not 3V, as 3V will compromise LTE radio performance. According to this post, it is only recommend for high speed GPIOs near the module on the right hand side.

  1. Why is this the case? Where is this documented? More information on what exactly the performance compromise is will certainly help so that we can decide what we need... 
  2. What is "the right hand side" of the module?

Our whole system is at 3.3V, so we would love to be able to run VDD and VDD_GPIO at 3.3V so that no level translators are needed. According to the abovementioned post however, we understand that VDD_GPIO is recommended at 1.8V while we can still run VDD at 3.3V. 

Can you please provide some more clarity on this as it is quite confusing?

Regards,

Frikkie

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  • 0

    If "the right hand side" is as indicated below, it seems as if "high speed GPIOs" are the debug lines:

    Are there then any truth in saying that if we wish to run in debug mode, we will have to run at VDD_GPIO = 1.8V. If we however run in release mode, we can run the system at VDD_GPIO = 3.3V?

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  • 0

    If "the right hand side" is as indicated below, it seems as if "high speed GPIOs" are the debug lines:

    Are there then any truth in saying that if we wish to run in debug mode, we will have to run at VDD_GPIO = 1.8V. If we however run in release mode, we can run the system at VDD_GPIO = 3.3V?

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  • +1 in reply to user105759

    Hi,

    You are right about the right side of the chip.

    There is a note given in the documentation.:
    "It is not recommended to use high voltage, high drive GPIO outputs (VOH,HDH and VOH,HDL) with high frequency, high capacitance loads unless needed, as this may increase noise level and affect radio receiver performance. High drive/high load should especially be avoided on GPIO pins close to the radio front end.". 
    There is more information available about VDD_GPIO. There is no limitations to using VDD_GPIO in its operational range (1.8 V - 3.6 V). It is recommended to use standard drive strength for minimizing EMI issues. As for EMI issues in general, they are usually driven by your own board design, antennas, etc. The effect of the voltage level (inside its operational range) should be negligible in practice as long as you don't  have continuous traffic in GPIO pins, which is anyway not typical.

    Best regards,
    Dejan

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