Power VDD monitoring

1. I can find that the time from VDD fall below to POFWARN event occur is not characterized, so I don't have any specific number for it, it is likely in the us range. I would expect a dip of 1ms to trigger it, the only figure we have is:
https://infocenter.nordicsemi.com/topic/ps_nrf52810/power.html#unique_1424210123 

Note: POFWARN is only active while chip is in active state, so VDD is not monitored while in sleep mode. Also, I would mention that if you do any flash operations (write or erase) and POFWARN event occurs during or before the flash operation, then the flash operations will simply be ignored by hardware, in such case the software may think flash operations occurs/completed, even if they did not. Due to these drawbacks you may consider using COMP instead to monitor VDD.

2. The BOR will trigger if VDD fall below 1.7V, the exact level will depend on the mode of operation (sleep or active) and small variation in process, but BOR will for sure always trigger before the chip malfunction in any way. You can find the range that BOR may occur in ths table:
https://infocenter.nordicsemi.com/topic/ps_nrf52810/power.html#unique_1677536352 

It's not possible to identify if BOR vs. POR was triggered after VDD rise above minimum operating conditions again, you can identify other reason reasons:
https://infocenter.nordicsemi.com/topic/ps_nrf52810/power.html#register.RESETREAS 

Best regards,
Kenneth

1. I can find that the time from VDD fall below to POFWARN event occur is not characterized, so I don't have any specific number for it, it is likely in the us range. I would expect a dip of 1ms to trigger it, the only figure we have is:
https://infocenter.nordicsemi.com/topic/ps_nrf52810/power.html#unique_1424210123 

Note: POFWARN is only active while chip is in active state, so VDD is not monitored while in sleep mode. Also, I would mention that if you do any flash operations (write or erase) and POFWARN event occurs during or before the flash operation, then the flash operations will simply be ignored by hardware, in such case the software may think flash operations occurs/completed, even if they did not. Due to these drawbacks you may consider using COMP instead to monitor VDD.

2. The BOR will trigger if VDD fall below 1.7V, the exact level will depend on the mode of operation (sleep or active) and small variation in process, but BOR will for sure always trigger before the chip malfunction in any way. You can find the range that BOR may occur in ths table:
https://infocenter.nordicsemi.com/topic/ps_nrf52810/power.html#unique_1677536352 

It's not possible to identify if BOR vs. POR was triggered after VDD rise above minimum operating conditions again, you can identify other reason reasons:
https://infocenter.nordicsemi.com/topic/ps_nrf52810/power.html#register.RESETREAS 

Best regards,
Kenneth

Hi Kenneth,

Thank you for your reply.

Is there a need to worry about the fluctuations on the VDD line if the device automatically resets when the voltage falls below 1.7 V ? Can I be sure that the device will never enter an 'undefined state' if voltage drops below 1.7V ?

The BOR will be triggered automatically if VDD fall below operating conditions, so you likely will get sporadic resets in this case, and while below operating conditions you may experience that pins are in a fixed level depending on what the application was doing with the GPIO's at the time BOR occured.

Kenneth

Perfect !! Thank you