Dip on VDD line

Hi,

The actual level BOR trigger will vary a bit, for instance depending on the mode of operation when VDD fall below normal operating conditions, see here for details:
https://infocenter.nordicsemi.com/topic/ps_nrf52810/power.html#unique_1677536352 

BOR will always trigger if VDD fall low enough that the chip may not continue to run as specified.

Best regards,
Kenneth

Hi,

Thank you for your reply.

I am sorry, I did not understand this.

Does this table mean that, if the voltage drops (above 1.2V in systemOFF  and 1.48V in systemON), a BOR happens, and the system will recover reliably ?

Doesn't the system recover if the voltage drop below 1.2V (let's say 1.0V) ? Does BOR happen in this case ?

Could you please clarify ? 

The voltage range specify which supply voltage level that BOR will trigger, it means BOR will trigger some place between 1.48 to 1.7V for system ON mode, the actual supply voltage level depend for instance of small variations in process. If supply voltage does not fall low enough to trigger BOR, then the code will execute as normal, if voltage level fall low enough for BOR to trigger, then the chip will start from beginning of main() when supply voltage rise again.

Kenneth

sorry for repeated questions.

Okay, which means that in either case, the device recovers and can never enter an undefined/corrupted state. Is that right ?

In our case too, a BOR/(restart from main) should have happened, and the device should have recovered/worked properly, as the voltage is dropping to 1.58V. Could you please guess what could go wrong here ?

The chip will either trigger BOR (= stop executing code and start from beginning of main() when power rise again) OR it will run as normal, there is no state between these two (= it can never enter an corrupted state).

However, have in mind that if you have any sensors connected, these sensors may also be reset at a different supply level, so have that in mind.

Kenneth

The chip will either trigger BOR (= stop executing code and start from beginning of main() when power rise again) OR it will run as normal, there is no state between these two (= it can never enter an corrupted state).

However, have in mind that if you have any sensors connected, these sensors may also be reset at a different supply level, so have that in mind.

Kenneth

Hi Kenneth, 

Thank you for your reply.

My application is pure beaconing application with an interval of 400ms. It doesn't have any sensors connected. After the dip I don't receive any beacons and when I checked with nRF sniffer I see that the packets are corrupted (CRC error). (Please note that I use solar beacon code for Nordic playground- github)

user2111 said:

if voltage level fall low enough for BOR to trigger

Can it be a possibility that the dip is too fast that the chip misses the dip and never do a BOR, can this happen ? If you see the snapshot, you can notice that the dip is too sharp. Also, are there any figures about the time it should stay below the operating voltage for BOR to happen ?

The solar beacon code is not qualified BLE stack.

In general I would say that large variations in VDD can impact the analog performance, such that for instance modulation are affected, this may impact the reception of the packet, however CRC error can also occur due to radio interference from wifi and/or other BT devices nearby. 

Kenneth

Hi Kenneth, 

Thank you for your reply.

user115812 said:

Can it be a possibility that the dip is too fast that the chip misses the dip and never do a BOR, can this happen ?

How fast is the processor sampling the VDD line ? What if the dip is faster than the sampling rate ?

It doesn't work that way, it's level triggered, either it's above or BOR will trigger, there is no intermediate state. That said though, I assume you have followed the reference schematic, layout and bill of materials.

Kenneth